Patent US5016222A successfully refreshed from Google Patents.
US5016222A
Expired / Lapsed
US
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Circuit responsive to a voltage change for detecting erroneous writing into a memory
Assignee: NEC Electronics Corp
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Filing: 1990-02-27
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Granted: 1991-05-14
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Expires: 2010-02-27
Abstract
Abstract A circuit for detecting a power supply voltage in a memory apparatus comprises a first circuit, through which flows a first saturating current which is constant when a power supply voltage is above a predetermined value, and a second circuit, through which flows a second current which increases in proportion to the power supply voltage when it is above the predetermined value. The first circuit includes an N-channel enhancement mode insulated gate field effect transistor ("NE-IGFET"), and the second circuit includes an N-channel depletion mode insulated gate field effect transistor ("ND-IGFET"). A power supply voltage is thus detected by responsive to a difference between the threshold values of the NE-IFGET and ND-IFGET, which is not dependent on a temperature.
Inventors
- 👤 Kiyokazu Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:26
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/143; G11C16/00; G11C16/02; G11C16/06; G11C16/30
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
237 words
A circuit for detecting a power supply voltage in a memory system, comprising: a first P-channel field-effect transistor having a source connected to a power supply, and a commonly connected gate and drain; an N-channel depletion mode field-effect transistor having a drain connected to said drain of said first P-channel field-effect transistor, and a gate and a source commonly connected to a ground; a turned on field-effect transistor having a gate and a source connected to said power supply; a first N-channel enhancement mode field-effect transistor having a drain and a gate commonly connected to a drain of said turned on field effect transistor and a source connected to the ground; a second P-channel field-effect transistor having a source connected to said power supply, a gate connected to a common node between said first P-channel field-effect transistor and said N-channel depletion mode field-effect transistor, and a drain connected to a voltage detecting node; a second N-channel enhancement mode field-effect transistor having a drain connected through said voltage detecting node to said drain of said second P-channel field-effect transistor, a gate connected to a common node between said turned on field-effect transistor and said first N-channel enhancement mode transistor, and a source connected to the ground; and an inverter connected between said power supply and the ground, and having an input terminal connected to said voltage detecting node and an output terminal for providing a voltage detected result.
Claim 2
Dependent Claim
237 words
A circuit for detecting a power supply voltage in a memory system, comprising: a first P-channel field-effect transistor having a source connected to a power supply, and a commonly connected gate and drain; an N-channel depletion mode field-effect transistor having a drain connected to said drain of said first P-channel field-effect transistor, and a gate and a source commonly connected to a ground; a turned on field-effect transistor having a gate and a source connected to said power supply; a first N-channel enhancement mode field-effect transistor having a drain and a gate commonly connected to a drain of said turned on field effect transistor and a source connected to the ground; a second P-channel field-effect transistor having a source connected to said power supply, a gate connected to a common node between said first P-channel field-effect transistor and said N-channel depletion mode field-effect transistor, and a drain connected to a voltage detecting node; a second N-channel enhancement mode field-effect transistor having a drain connected through said voltage detecting node to said drain of said second P-channel field-effect transistor, a gate connected to a common node between said turned on field-effect transistor and said first N-channel enhancement mode transistor, and a source connected to the ground; and an inverter connected between said power supply and the ground, and having an input terminal connected to said voltage detecting node and an output terminal for providing a voltage detected result.
Claim 3
Dependent Claim
59 words
A circuit for detecting a power supply voltage in a memory system, according to claim 1, wherein: an equivalent resistance of said N-channel depletion mode field-effect transistor is larger than that of said first P-channel field-effect transistor; and an equivalent resistance of said first N-channel enhancement mode field-effect transistor is larger than that of said turned-on field effect transistor.
Claim 4
Dependent Claim
51 words
A circuit for detecting a power supply voltage in a memory system, according to claim 1, wherein: said first P-channel field-effect transistor is of an enhancement mode type; said turned-on field-effect transistor is an N-channel depletion mode field-effect transistor; and said second P-channel field-effect transistor is of an enhancement mode type.
References Cited (Backward Citations)
JPS54106134A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-05-13 | 1994-11-12 | 1995-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-13 | 1998-11-12 | 1999-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-13 | 2002-11-12 | 2003-05-14 | $7700.00 | Window Closed / Lapsed |