Lossless snubber circuit

Claim 2

A snubber circuit for a power switch having main current path electrodes and a control electrode and alternately operated in on and off states in response to a gating signal, comprising: a capacitor coupled across the main current path electrodes; an inductor having a first end coupled to one of the main current path electrodes of the power switch and a second end; a controllable switch operable in on and off states and having a first main current path electrode coupled to the second end of the inductor, a second main current path electrode coupled to the other main current path electrode of the power switch and a control electrode; and means coupled to the control electrodes of the power switch and the controllable switch and responsive to the gating signal and a voltage across the main current path electrodes of the power switch for operating the switches whereby the controllable switch is turned on when the gating signal is commanding turn on of the power switch and the voltage across the main current path electrodes of the power switch is above a certain level so that the capacitor is discharged through the inductor and whereby the controllable switch is subsequently turned off and the power switch turned on when the gating signal is commanding turn-on of the latter switch and the voltage across the main current path electrodes thereof falls below the certain level.

Claim 3

The snubber circuit of claim 1, whereby the operating means comprises a control circuit including a logic gate which prevents turn-on of the power switch when the voltage across the main current path electrodes of such switch is above the certain level.

Claim 4

The snubber circuit of claim 2, wherein the logic gate comprises a NAND gate which receives the gating signal and a signal representing the voltage across the main current path electrodes of the power switch.

Claim 5

The snubber circuit of claim 1, wherein the operating means includes a logic gate which controls the controllable switch and which receives the gating signal and a signal representing the voltage across the main current path electrodes of the power switch.

Claim 6

The snubber circuit of claim 4, wherein the logic gate comprises a NAND gate.

Claim 7

The snubber circuit of claim 4, wherein the operating means further includes a pulse transformer coupled between the logic gate and the control electrode of the controllable switch.

Claim 8

A power converter, comprising: a transistor having a collector, an emitter and a base and operated in response to a gating signal; a snubber circuit coupled to the transistor including a capacitor coupled across the collector and emitter, an inductor having a first end coupled to one of the collector and emitter and a second end and a controllable switch operable in on and off states and having a first main current path electrode coupled to the second end of the inductor, a second main current path electrode coupled to the other of the collector and emitter of the transistor and a control electrode; and a control circuit coupled to the base of the transistor and the control electrode of the controllable switch and responsive to the gating signal and a voltage V CE1 across the collector and emitter of the transistor for operating the transistor and the controllable switch whereby the controllable switch is turned on and the transistor is prevented from turning on when the gating signal is commanding turn-on of the transistor and the voltage V CE1 is above a certain level so that the capacitor is discharged through the inductor and whereby the controllable switch is subsequently turned off and the transistor turned on when the gating signal is commanding turn on of the transistor and the voltage V CE1 falls below the certain level.

Claim 9

A power converter, comprising: a transistor having a collector, an emitter and a base and operated in response to a gating signal; a snubber circuit coupled to the transistor including a capacitor coupled across the collector and emitter, an inductor having a first end coupled to one of the collector and emitter and a second end and a controllable switch operable in on and off states and having a first main current path electrode coupled to the second end of the inductor, a second main current path electrode coupled to the other of the collector and emitter of the transistor and a control electrode; and a control circuit coupled to the base of the transistor and the control electrode of the controllable switch and responsive to the gating signal and a voltage V CE1 across the collector and emitter of the transistor for operating the transistor and the controllable switch whereby the controllable switch is turned on and the transistor is prevented from turning on when the gating signal is commanding turn-on of the transistor and the voltage V CE1 is above a certain level so that the capacitor is discharged through the inductor and whereby the controllable switch is subsequently turned off and the transistor turned on when the gating signal is commanding turn on of the transistor and the voltage V CE1 falls below the certain level.

Claim 10

The power converter of claim 7, wherein the transistor collector is coupled to a first DC potential and further including a second transistor having a base, a collector coupled to the emitter of the first-named transistor at a junction there between and an emitter coupled to a second DC potential and wherein a second snubber circuit is coupled across the collector and emitter of the second transistor and a second control circuit is coupled to the base of the second transistor and is responsive to a second gating signal which comprises an inverted version of the first-named gating signal.

Claim 11

The power converter of claim 8, wherein the first end of the inductor is coupled to the junction between the transistors and wherein the second snubber circuit includes a second capacitor coupled across the collector and emitter of the second transistor and a second controllable switch operable in on and off states and having a first main current path electrode coupled to the first DC potential, a second main current path electrode coupled to the second end of the inductor and a control electrode and wherein the second control circuit is coupled to the base of the second transistor and the control electrode of the second controllable switch and is further responsive to a voltage V CE2 across the collector and emitter of the second transistor for operating the second transistor and the second controllable switch whereby the second controllable switch is turned on and the second transistor is prevented from turning on when the second gating signal is commanding turn-on of the second transistor and the voltage V CE2 is above a second certain level so that the second capacitor is discharged through the inductor and whereby the second controllable switch is subsequently turned off and the second transistor turned on when the second gating signal is commanding turn-on of the second transistor and the voltage V CE2 falls below the second certain level so that a shoot-through condition caused by simultaneous conduction of the transistors is prevented.