Waveshaping subsystem using converter and delay lines

Claim 2

A circuit for shaping waveforms, comprising: a plurality of delay elements, said delay elements being serially connected, with taps, to drive plural control lines at predetermined substantially nonoverlapping sequential times, a voltage generator circuit, connected to receive said control lines, and configured to output a voltage which is selected, in accordance with the instantaneous state of said control lines, from plural predetermined possible voltages; wherein plural ones of said delay elements have adjustable delay characteristics.

Claim 3

The circuit of claim 1, wherein said voltage generator circuit comprises an analog to digital converter circuit, and said control lines comprise digital bits of input thereto.

Claim 4

The circuit of claim 1, wherein said voltage generator circuit generates complementary bipolar outputs in response to the signals on said control lines.

Claim 5

The circuit of claim 1, wherein plural ones of said delay elements each include capacitors which can be trimmed to change a time constant thereof.

Claim 6

The circuit of claim 1, wherein plural ones of said delay elements each have a programmable delay time.

Claim 7

The circuit of claim 1, wherein a clock signal is applied as an input to said plurality of delay elements.

Claim 8

The circuit of claim 1, wherein of said taps of said delay elements are logically combined to provide a clock signal to a counter, and the count value output of said counter provides a multibit input to said voltage generator circuit.

Claim 9

The circuit of claim 1, wherein at least one of said taps of said delay elements are connected through a respective one-shot circuit.

Claim 10

A transmit line interface unit, comprising: a plurality of delay elements, said delay elements being serially connected, with taps, to drive plural control lines at predetermined substantially nonoverlapping sequential times; a voltage generator circuit, connected to receive said control lines, and configured to output a voltage which is selected, in accordance with the instantaneous state of said control lines, from plural predetermined possible voltages; wherein plural ones of said delay elements have adjustable delay characteristics; and wherein said predetermined possible voltages, and a control relation of said control lines to said voltage generator circuit, are predefined so that a user can select a waveform, consisting of voltage levels selected from said predetermined possible voltages separated by time delays defined by said delay elements, which provide the output waveform specified by a communications interface standard.

Claim 11

A transmit line interface unit, comprising: a plurality of delay elements, said delay elements being serially connected, with taps, to drive plural control lines at predetermined substantially nonoverlapping sequential times; a voltage generator circuit, connected to receive said control lines, and configured to output a voltage which is selected, in accordance with the instantaneous state of said control lines, from plural predetermined possible voltages; wherein plural ones of said delay elements have adjustable delay characteristics; and wherein said predetermined possible voltages, and a control relation of said control lines to said voltage generator circuit, are predefined so that a user can select a waveform, consisting of voltage levels selected from said predetermined possible voltages separated by time delays defined by said delay elements, which provide the output waveform specified by a communications interface standard.

Claim 12

The unit of claim 9, wherein said voltage generator circuit comprises an analog to digital converter circuit, and said control lines comprise digital bits of input thereto.

Claim 13

The unit of claim 9, wherein said voltage generator circuit generates complementary bipolar outputs in response to the signals on said control lines.

Claim 14

The unit of claim 9, wherein plural ones of said delay elements each include capacitors which can be trimmed to change a time constant thereof.

Claim 15

The unit of claim 9, wherein plural ones of said delay elements each have a programmable delay time.

Claim 16

The unit of claim 9, wherein a clock signal is applied as an input to said plurality of delay elements.

Claim 17

The unit of claim 9, wherein said communications interface standard is T1.

Claim 18

The unit of claim 9, wherein said communications interface standard is CEPT.

Claim 21

The method of claim 17, wherein plural ones of said delay elements each include capacitors which can be trimmed to change a time constant thereof.

Claim 22

The method of claim 17, wherein plural ones of said delay elements each have a programmable delay time.

Claim 23

The method of claim 17, wherein a clock signal is applied as an input to said plurality of delay elements.

Claim 24

The method of claim 17, wherein said communications interface standard is T1.

Claim 25

The method of claim 17, wherein said communications interface standard is CEPT.

Claim 26

The method of claim 17, wherein said voltage generator circuit comprises an analog to digital converter circuit, and said control lines comprise digital bits of input thereto.