Integral switched capacitor FIR filter/digital-to-analog converter for sigma-delta encoded digital audio

Claim 1

In an integrated circuit, a circuit for converting single bit digital input data into analog form, characterized by: a shift register, having N-taps, for shifting the digital input data; a plurality of signal capacitors, corresponding to the taps on the shift register, each signal capacitor having a predetermined capacitance and one end coupling to a summing node; and, a 2×2 switch, responsive to the corresponding tap on the shift register, having two inputs for selectively coupling one of two voltage references to the other end of the signal capacitors depending on the state of the corresponding tap of the shift register and two outputs; a 2:1 switch for coupling the corresponding one of the plurality of signal capacitors to either of the outputs of the 2×2 switch in response to the state of a clock signal; wherein signals on the summing node are analog signals corresponding to the digital input data and the capacitances of the signal capacitors represent corresponding tap weight coefficients of a finite impulse response filter.

Claim 5

A method of converting single bit digital input data into analog form characterized by the steps of: shifting the digital input data with a multiple tap shift register; summing to a summing node charge from a plurality of signal capacitors, corresponding to the taps on the shift register, each signal capacitor having a predetermined capacitance; and, switching with a 2×2 switch, in response to the corresponding tap of the shift register, one of two voltage references between two outputs of the 2×2 switch depending on the state of the corresponding tap of the shift register; and, switching the corresponding signal capacitor between the two outputs of the 2×2 switch in response to a clock signal; wherein signals on the summing node are analog signals corresponding to the digital input data and the capacitances of the signal capacitors represent corresponding tap weight coefficients of a finite impulse response filter.

Claim 6

A method of converting single bit digital input data into analog form characterized by the steps of: shifting the digital input data with a multiple tap shift register; summing to a summing node charge from a plurality of signal capacitors, corresponding to the taps on the shift register, each signal capacitor having a predetermined capacitance; and, switching with a 2×2 switch, in response to the corresponding tap of the shift register, one of two voltage references between two outputs of the 2×2 switch depending on the state of the corresponding tap of the shift register; and, switching the corresponding signal capacitor between the two outputs of the 2×2 switch in response to a clock signal; wherein signals on the summing node are analog signals corresponding to the digital input data and the capacitances of the signal capacitors represent corresponding tap weight coefficients of a finite impulse response filter.

Claim 8

A method of determining the number of taps and the tap weight coefficients in a filter adapted to filter over-sampled data, characterized by the steps of: generating a digital data stream from an encoder, used to encode the over-sampled data, with no signal input; generating a sampled signal representing the passband of the desired filter; combining the digital data stream and the sampled signal; filtering the combined digital data stream and the sampled signal by the filter; subtracting the output of the filter from a delayed version of the sampled signal to form an error signal, the amount of delay being substantially the same as the delay through the filter; and, adjusting the number of taps and the tap weight coefficients of the filter to reduce the error signal.

Claim 9

A method of determining the number of taps and the tap weight coefficients in a filter adapted to filter over-sampled data, characterized by the steps of: generating a digital data stream from an encoder, used to encode the over-sampled data, with no signal input; generating a sampled signal representing the passband of the desired filter; combining the digital data stream and the sampled signal; filtering the combined digital data stream and the sampled signal by the filter; subtracting the output of the filter from a delayed version of the sampled signal to form an error signal, the amount of delay being substantially the same as the delay through the filter; and, adjusting the number of taps and the tap weight coefficients of the filter to reduce the error signal.