US5012242A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input data processor for D/A converter utilizing dithering
Assignee: Pioneer Corp
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Filing: 1990-03-12
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Granted: 1991-04-30
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Expires: 2010-03-12
Abstract
Abstract An input data processor of the present invention has a dither signal adder for adding a dither signal to digital data which corresponds to an alternating signal of the type which crosses the zero level each time the alternating signal varies from a maximum to a minimum (i.e., positive max to negative max). The resultant signal of the digital signal added to the dither signal is sent to a level shift circuit which shifts the digital data output from the adder to a positive or negative level, which has sufficient magnitude to prevent the signal from crossing the zero level during variation from max to min. By eliminating zero crossing with this shifting operation, the present invention prevents inversion of the MSB of the digital signal, which also prevents glitches in the analog output. These glitches were previously caused by inversion of the MSB.
Inventors
- 👤 Junichi Yoshio
- 👤 Masami Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:57
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0636; H03M1/0639; H03M1/0641; H03M1/08; H03M1/0863; H03M1/66
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
87 words
An input data processor for a D/A converter for processing digital data which is input to a D/A converter, said digital data corresponding to an alternating signal of the type which crosses a zero level, said processor comprising: a dither signal adder for adding a dither signal to said digital signal, and to provide a dithered digital signal; and a level shift circuit for shifting a level of said dithered digital signal, by an amount sufficient to prevent said dithered digital signal from crossing said zero level.
Claim 2
Dependent Claim
87 words
An input data processor for a D/A converter for processing digital data which is input to a D/A converter, said digital data corresponding to an alternating signal of the type which crosses a zero level, said processor comprising: a dither signal adder for adding a dither signal to said digital signal, and to provide a dithered digital signal; and a level shift circuit for shifting a level of said dithered digital signal, by an amount sufficient to prevent said dithered digital signal from crossing said zero level.
Claim 3
Dependent Claim
33 words
An input data processor according to claim 1, further comprising an attenuator for attenuating said digital data input to said dither signal adder at least by the signal level of said dither signal.
Claim 4
Dependent Claim
24 words
An input data processor according to claim 1, wherein said dither signal is a signal having an analogue waveform expressed by a periodic function.
Claim 5
Dependent Claim
100 words
An input data processor for an D/A converter for processing digital data which is input to a D/A converter, said digital data corresponding to an alternating signal of the type which crosses a zero level, said processor comprising: a dither signal adder for adding a dither signal to said digital signal and to provide a dithered digital signal; and a data length converter for compressing the data length of said dithered digital signal; and a level shift circuit for shifting said compressed dithered digital signal by an amount sufficient to prevent said dithered digital signal from crossing said zero level.
Claim 6
Dependent Claim
100 words
An input data processor for an D/A converter for processing digital data which is input to a D/A converter, said digital data corresponding to an alternating signal of the type which crosses a zero level, said processor comprising: a dither signal adder for adding a dither signal to said digital signal and to provide a dithered digital signal; and a data length converter for compressing the data length of said dithered digital signal; and a level shift circuit for shifting said compressed dithered digital signal by an amount sufficient to prevent said dithered digital signal from crossing said zero level.
Claim 7
Dependent Claim
33 words
An input data processor according to claim 4, further comprising an attenuator for attenuating said digital data input to said dither signal adder at least by the signal level of said dither signal.
References Cited (Backward Citations)
US4857927A
Cited
US4937576A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |