US4937576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dither circuit responsive to zero input signal level
Assignee: Pioneer Corp
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Filing: 1989-11-22
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Granted: 1990-06-26
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Expires: 2009-11-22
Abstract
Abstract A dither circuit including an adder for receiving an input signal and a dither signal which is generated by a dither signal generator, a level detection circuit for detecting the signal level of the input signal, and a dither control circuit for stopping the feeding of the dither signal to the adder when the level detection circuit detects that the signal level of the input signal is zero.
Inventors
- 👤 Junichi Yoshio
- 👤 Masami Suzuki
- 👤 Masami Tsuchida
- 👤 Kiyoshi Iwai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:25
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0634; H03M1/0636; H03M1/0639; H03M1/0641; H03M1/66
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
68 words
A dither circuit comprising: a dither generator for generating a dither signal; an adder for mixing said dither signal into an input signal and providing an adder output signal; a level detection circuit for detecting the signal level of said input signal; and a dither control circuit for stopping the feeding of said dither signal to said adder when the signal level of said input signal is zero.
Claim 2
Dependent Claim
68 words
A dither circuit comprising: a dither generator for generating a dither signal; an adder for mixing said dither signal into an input signal and providing an adder output signal; a level detection circuit for detecting the signal level of said input signal; and a dither control circuit for stopping the feeding of said dither signal to said adder when the signal level of said input signal is zero.
Claim 3
Dependent Claim
60 words
The dither circuit as defined in claim 1, further comprising a first D/A converter for converting said adder output signal of said adder to a first analog signal, a second D/A converter for converting said dither signal of said dither generator to a second analog signal, and a subtractor for subtracting said second analog signal from said first analog signal.
Claim 4
Dependent Claim
35 words
The dither circuit as defined in claim 1, wherein said dither control circuit includes means for generating a control signal which disables said dither generator when the signal level of said input signal is zero.
Claim 5
Dependent Claim
115 words
A dither circuit comprising: a digital filter for removing digital noise in a digital signal sampled at a predetermined sampling frequency and providing a filter output signal; a dither generator for generating a dither signal; an adder for mixing said dither signal into said filter output signal of said digital filter and providing an adder output signal; a D/A converter for converting said adder output signal of said adder into an analog signal; a level detection circuit for detecting the signal level of said filter output signal of said digital filter; and a dither control circuit for stopping the feeding of said dither signal to said adder when said filter output signal level is zero.
Claim 6
Dependent Claim
115 words
A dither circuit comprising: a digital filter for removing digital noise in a digital signal sampled at a predetermined sampling frequency and providing a filter output signal; a dither generator for generating a dither signal; an adder for mixing said dither signal into said filter output signal of said digital filter and providing an adder output signal; a D/A converter for converting said adder output signal of said adder into an analog signal; a level detection circuit for detecting the signal level of said filter output signal of said digital filter; and a dither control circuit for stopping the feeding of said dither signal to said adder when said filter output signal level is zero.
Claim 7
Dependent Claim
65 words
The dither circuit as defined in claim 4, further comprising switching means coupled between an input of said adder and said dither generator, said switching means switching between a closed state for allowing said dither signal of said dither generator to be fed to said adder and an open state for preventing said dither signal of said dither generator to be fed to said adder.
Claim 8
Dependent Claim
35 words
The dither circuit as defined in claim 5, wherein said dither control circuit generates a control signal, and wherein said switching means switches between said open and closed states in accordance with said control signal.
Claim 9
Dependent Claim
17 words
The dither circuit as defined in claim 4, wherein said dither generator is a sine-wave dither generator.
Claim 10
Dependent Claim
30 words
The dither circuit as defined in claim 4, wherein said digital filter, adder, dither generator, level detection circuit and said dither control circuit together constitute a large scale integration circuit.
Claim 11
Dependent Claim
81 words
A dither circuit comprising: a dither generator for generating a dither signal; an adder for mixing said dither signal into an analog input signal; an A/D converter for converting said adder output signal of said adder into a digital signal; a level detection circuit for detecting the signal level of said analog input signal; and a dither control circuit for stopping the feeding of said dither signal to said adder then the signal level of said analog input signal is zero.
Claim 12
Dependent Claim
81 words
A dither circuit comprising: a dither generator for generating a dither signal; an adder for mixing said dither signal into an analog input signal; an A/D converter for converting said adder output signal of said adder into a digital signal; a level detection circuit for detecting the signal level of said analog input signal; and a dither control circuit for stopping the feeding of said dither signal to said adder then the signal level of said analog input signal is zero.
Claim 13
Dependent Claim
106 words
A dither circuit comprising: a digital filter for removing digital noise in a digital signal sampled at a predetermine sampling frequency and providing a filter output signal; an attenuator for attenuating said filter output of said digital filter and providing an attenuator output signal; a dither generator for generating a dither signal; an adder for mixing said dither signal into said attenuator output signal of said attenuator; a level detection circuit for detecting the signal level of said attenuator output signal of said attenuator; and a dither control circuit for stopping the feeding of said dither signal to said adder when said signal level is zero.
Claim 14
Dependent Claim
106 words
A dither circuit comprising: a digital filter for removing digital noise in a digital signal sampled at a predetermine sampling frequency and providing a filter output signal; an attenuator for attenuating said filter output of said digital filter and providing an attenuator output signal; a dither generator for generating a dither signal; an adder for mixing said dither signal into said attenuator output signal of said attenuator; a level detection circuit for detecting the signal level of said attenuator output signal of said attenuator; and a dither control circuit for stopping the feeding of said dither signal to said adder when said signal level is zero.
Claim 15
Dependent Claim
27 words
The dither control circuit as defined in claim 10, further comprising a D/A converter for converting said adder output signal of said adder into an analog signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-25 | 1993-12-25 | 1994-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-25 | 1997-12-25 | 1998-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-25 | 2001-12-25 | 2002-06-26 | $7700.00 | Window Closed / Lapsed |