US5012240A
Expired / Lapsed
US
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Parallel to serial converter with complementary bit insertion for disparity reduction
Assignee: Toshiba Corp
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Filing: 1990-06-26
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Granted: 1991-04-30
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Expires: 2010-06-26
Abstract
Abstract A signal conversion circuit is used to convert a parallel signal to a serial signal and comprises a parallel input/serial output type of shift register having input terminals corresponding in number to at least n+k bits (n and k: integer), an inverting circuit and a timing circuit. The n-bit input parallel signal is applied to n successive input terminals of the shift register and k bit of the n-bit parallel signal is inverted by the inverting circuit to be applied to the remaining k input terminal of the shift register. The (n+k)-bit parallel signal loaded into the shift register is serially output at a predetermined rate by the timing circuit to provide a serial signal.
Inventors
- 👤 Shoichi Takahashi
- 👤 Sayohiko Ichiki
- 👤 Masatoshi Yorozu
- 👤 Seiji Kunishige
- 👤 Taro Shibagaki
- 👤 Fumihiko Shimizu
- 👤 Fumio Fujioka
- 👤 Toshinori Kondo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:55
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03866; H03; H03M; H03M9/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
188 words
A signal conversion circuit comprising: parallel input/serial output type of shift register means supplied with an input signal having a first number (n) of bits for converting a parallel signal to a serial signal the parallel signal containing the input data and constituted by a second predetermined number (n+k) of bits which is at least one (k) bit more than the first predetermined number (n), said shift register means having at least the second predetermined number of input terminals (n+k), and the first predetermined number (n) of successive input terminals of said shift register means being supplied with the input signal; inverting circuit means for inverting at least one bit of the input signal to apply an inverted bit signal to at least one of the input terminals of the shift register means; and timing circuit means for providing to the shift register means a first timing signal for permitting the input signal and the inverted signal to be loaded into the shift register means and a second timing signal for permitting the loaded signal to be read out of the shift register means at a predetermined rate.
Claim 2
Dependent Claim
188 words
A signal conversion circuit comprising: parallel input/serial output type of shift register means supplied with an input signal having a first number (n) of bits for converting a parallel signal to a serial signal the parallel signal containing the input data and constituted by a second predetermined number (n+k) of bits which is at least one (k) bit more than the first predetermined number (n), said shift register means having at least the second predetermined number of input terminals (n+k), and the first predetermined number (n) of successive input terminals of said shift register means being supplied with the input signal; inverting circuit means for inverting at least one bit of the input signal to apply an inverted bit signal to at least one of the input terminals of the shift register means; and timing circuit means for providing to the shift register means a first timing signal for permitting the input signal and the inverted signal to be loaded into the shift register means and a second timing signal for permitting the loaded signal to be read out of the shift register means at a predetermined rate.
Claim 3
Dependent Claim
52 words
A signal conversion circuit according to claim 1, in which the shift register means has an LSB input terminal corresponding to the least significant bit (LSB), and in which said inverting circuit means comprises an inverter for applying the inverted bit signal to the LSB input terminal of the shift register means.
Claim 4
Dependent Claim
91 words
A signal conversion circuit according to claim 1, in which said timing circuit means receives a first clock signal having a frequency corresponding to a transmission rate of the serial signal and a second clock signal having a lower frequency than the first clock signal and comprises a flip-flop means for latching the second clock signal in synchronization with the first clock signal and a logic gate means for performing a logical operation on the second clock signal and an output of the flip-flop means to produce the second timing signal.
Claim 5
Dependent Claim
123 words
A signal conversion circuit comprising: complementary code inserting means supplied with an original data signal having a first number (n) of bits for converting a first data signal to a second data signal, the first data signal containing the original data signal and constituted by a second number (n+k) of bits which is at least one (k) bit more than the first number (n) of bits, and for inserting a complementary code into the one bit to provide an output data signal; and scrambling means for generating a pseudo-randam code for retaining the complementary code rule of the output data form the complementary code inserting means and scrambling the output data from the complementary code inserting means in accordance with the pseudorandom code.
Claim 6
Dependent Claim
123 words
A signal conversion circuit comprising: complementary code inserting means supplied with an original data signal having a first number (n) of bits for converting a first data signal to a second data signal, the first data signal containing the original data signal and constituted by a second number (n+k) of bits which is at least one (k) bit more than the first number (n) of bits, and for inserting a complementary code into the one bit to provide an output data signal; and scrambling means for generating a pseudo-randam code for retaining the complementary code rule of the output data form the complementary code inserting means and scrambling the output data from the complementary code inserting means in accordance with the pseudorandom code.
Claim 7
Dependent Claim
166 words
A signal conversion circuit according to claim 4, in which said complementary code inserting means comprises: parallel input/serial output type of shift register means for converting a parallel signal corresponding to the first data signal to a serial signal corresponding to the second data signal, the shift register means having at least the second predetermined number (n+k) of input terminals, and the first predetermined number (n) of successive input terminals of said shift register means being supplied with the parallel signal; inverting circuit means for inverting at least one bit of the parallel signal to apply inverted bit signal to the remainder of the input signals of the shift register means; and timing circuit means for providing to the shift register means a first timing signal for permitting the parallel signal and the inverted signal to be loaded into the shift register means and a second timing signal for permitting the loaded signal to be read out of the shift register means at a predetermined rate.
Claim 8
Dependent Claim
64 words
A signal conversion circuit according to claim 4, in which said scrambling means comprises an M series generator for generating a pseudo-random pulse train, a control circuit for controlling the operation of the M series generator and an exclusive OR circuit for exclusive ORing the data output from the complementary code inserting means and the pseudo-random pulse train MP from the M series generator.
Claim 9
Dependent Claim
59 words
A signal conversion circuit according to claim 6, in which the control circuit comprises a flip-flop for delaying a load signal generated from the complementary code inserting circuit by one bit time and inverting it to provide an inverted signal and an AND gate responsive to the inverted signal to provide a control clock to the M series generator.
Claim 10
Dependent Claim
33 words
A signal conversion circuit according to claim 4, in which said scrambling means comprises a self-synchronizing type of scrambling circuit for scrambling the output data of the complementary code inserting means by self-synchronization.
Claim 11
Dependent Claim
105 words
A signal conversion circuit for converting a (n+k)-bit parallel signal (n and k: integer) containing an n-bit input signal to a serial signal comprising: a parallel input/serial output type of shift register having input terminals corresponding in number to at least (n+k) bits and receiving the parallel signal at its n successive input terminals; an inverting circuit for inverting at least one (k) bit of the n-bit parallel signal and applying the inverted bit to the remaining k input terminal of the shift register; and timing circuit for allowing the (n+k)-bit parallel signal to be serially output from the shift register at a predetermined rate
Claim 12
Dependent Claim
105 words
A signal conversion circuit for converting a (n+k)-bit parallel signal (n and k: integer) containing an n-bit input signal to a serial signal comprising: a parallel input/serial output type of shift register having input terminals corresponding in number to at least (n+k) bits and receiving the parallel signal at its n successive input terminals; an inverting circuit for inverting at least one (k) bit of the n-bit parallel signal and applying the inverted bit to the remaining k input terminal of the shift register; and timing circuit for allowing the (n+k)-bit parallel signal to be serially output from the shift register at a predetermined rate
Claim 13
Dependent Claim
85 words
A signal conversion circuit comprising: complementary code inserting means for converting a first data containing input data of n-bits (n: integer) and constituted by n bits plus at least one bit to a second data and for inserting a complementary code into the one bit; and scrambling means for generating a pseudo-random code to retain the complementary code rule in output data from the complementary code inserting means and scrambling the output data from the complementary code inserting means in accordance with the pseudo-random code.
Claim 14
Dependent Claim
85 words
A signal conversion circuit comprising: complementary code inserting means for converting a first data containing input data of n-bits (n: integer) and constituted by n bits plus at least one bit to a second data and for inserting a complementary code into the one bit; and scrambling means for generating a pseudo-random code to retain the complementary code rule in output data from the complementary code inserting means and scrambling the output data from the complementary code inserting means in accordance with the pseudo-random code.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-29 | 1994-10-29 | 1995-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-29 | 1998-10-29 | 1999-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-29 | 2002-10-29 | 2003-04-30 | $7700.00 | Window Closed / Lapsed |