Semiconductor memory device with two storage nodes

Claim 2

A semiconductor memory device comprising a p-type semiconductor substrate (1) having a planar surface, a trench (16) formed on said planar surface and having side walls and a bottom surface, a first region (19) of a capacitor cell plate formed of an n-type impurity layer on the side walls and the bottom surface of said trench, two capacitor storage nodes (2a) having the surfaces thereof covered by capacitor dielectric films (7a and 8a) and formed along the side walls of said trench for facing to each other, a second region (3a) of said cell plate formed of an electrically conductive material, said second region being interposed between said two storage nodes (2a) and connected to said first region (19) of the cell plate at the bottom surface of said trench (16), and n-channel type field effect transistors (9, 10, 12, 18 and 28) each connected to one of said storage nodes (2a) and formed on said planar surface.

Claim 3

A semiconductor memory device comprising a p-type semiconductor substrate (1) having a planar surface, a trench (16) formed on said planar surface and having side walls and a bottom surface, a first region (19) of a capacitor cell plate formed of an n-type impurity layer on the side walls and the bottom surface of said trench. two capacitor storage nodes (2a) having the surfaces thereof covered by capacitor dielectric films (7a and 8a) and formed along the side walls of said trench for facing to each other, a second region (3a) of said cell plate formed of an electrically conductive material, said second region being interposed between said two storage nodes (2a) and connected to said first region (19) of the cell plate at the bottom surface of said trench (16), and n-channel type field effect transistors (9, 10, 12, 18 and 28) each connected to one of said storage nodes (2a) and formed on said planar surface, wherein said field effect transistors (9, 10, 12, 18, 28) each includes a source region (9), a thick interlayer insulating film (27a) is formed between the first region (19) of the cell plate and the source region (9) on said planar surface, and the storage nodes (2a) and the source region (9) are electrically connected to each other over said thick interlayer insulating film (27a) so that the insulating film (27a) also acts as an isolation film between the first region (19) of the cell plate and the source region (9).

Claim 4

A semiconductor memory device comprising a p-type semiconductor substrate (1) having a planar surface, a trench (16) formed on said planar surface and having side walls and a bottom surface, a first region (19) of a capacitor cell plate formed of an n-type impurity layer on the side walls and the bottom surface of said trench. two capacitor storage nodes (2a) having the surfaces thereof covered by capacitor dielectric films (7a and 8a) and formed along the side walls of said trench for facing to each other, a second region (3a) of said cell plate formed of an electrically conductive material, said second region being interposed between said two storage nodes (2a) and connected to said first region (19) of the cell plate at the bottom surface of said trench (16), and n-channel type field effect transistors (9, 10, 12, 18 and 28) each connected to one of said storage nodes (2a) and formed on said planar surface, wherein said field effect transistors (9, 10, 12, 18, 28) each includes a source region (9), a thick interlayer insulating film (27a) is formed between the first region (19) of the cell plate and the source region (9) on said planar surface, and the storage nodes (2a) and the source region (9) are electrically connected to each other over said thick interlayer insulating film (27a) so that the insulating film (27a) also acts as an isolation film between the first region (19) of the cell plate and the source region (9).

Claim 5

A semiconductor memory device according to claim 1, wherein said pair of storage nodes are each insulated from said first region (19) of the cell plate by said dielectric film (7a) and from said second region (3a) of said cell plate by said dielectric film (8a).

Claim 6

A semiconductor memory device according to claim 3, wherein said capacitor storage nodes (2a) are formed of an electrically conductive material and are insulated from said first region (19) of the cell plate at the bottom surface of said trench.

Claim 7

A semiconductor memory device according to claim 1, wherein said capacitor storage nodes (2a) are formed of an electrically conductive material and are insulated from said first region (19) of the cell plate at the bottom surface of said trench.

Claim 8

A semiconductor memory device according to claim 1 wherein said first and second regions of said cell plate are electrically connected to enable use of plural surfaces of said storage nodes for storage.

Claim 9

A semiconductor memory device comprising: a first conductivity type semiconductor substrate (1) having a planar surface, a trench (16) formed on said planar surface and having side walls and a bottom surface, a first region (19) of a capacitor cell plate formed of a second conductivity type layer on the side walls and the bottom surface of said trench, two capacitor storage nodes (2a) each having first and second surfaces thereof covered by respective capacitor dielectric films (7a and 8a) and formed along the side walls of said trench, said two storage nodes facing each other, a second region (3a) of said cell plate formed of an electrically conductive material, said second region being interposed between said two storage nodes (2a) and electrically connected to said first region (19) of the cell plate at the bottom surface of said trench (16), and field effect transistors (9, 10, 12, 18 and 28) each connected to one of said storage nodes (2a) and formed on said planar surface.

Claim 10

A semiconductor memory device comprising: a first conductivity type semiconductor substrate (1) having a planar surface, a trench (16) formed on said planar surface and having side walls and a bottom surface, a first region (19) of a capacitor cell plate formed of a second conductivity type layer on the side walls and the bottom surface of said trench, two capacitor storage nodes (2a) each having first and second surfaces thereof covered by respective capacitor dielectric films (7a and 8a) and formed along the side walls of said trench, said two storage nodes facing each other, a second region (3a) of said cell plate formed of an electrically conductive material, said second region being interposed between said two storage nodes (2a) and electrically connected to said first region (19) of the cell plate at the bottom surface of said trench (16), and field effect transistors (9, 10, 12, 18 and 28) each connected to one of said storage nodes (2a) and formed on said planar surface.

Claim 11

A semiconductor memory device according to claim 7 wherein said sidewalls of said trench (16) are in a substantially opposing relationship and said two storage nodes (2a) formed along said opposing sidewalls thereby face each other in an opposing relationship.

Claim 12

A semiconductor memory device according to claim 8 wherein said dielectric films (8a) cover interior opposing surfaces of said opposing storage nodes (2a) and said dielectric films (7a) cover outer surfaces of said opposing storage nodes (2a) facing said sidewalls of said trench (16).

Claim 13

A semiconductor memory device according to claim 9 wherein said dielectric films (7a) contact said first region (19) on the sidewalls of said trench (16).

Claim 14

A semiconductor memory device according to claim 9 wherein said dielectric films (7a) further cover bottom surfaces of said opposing storage nodes (2a) facing said bottom surface of said trench (16).

Claim 15

A semiconductor memory device according to claim 11 wherein said dielectric films (7a) contact said first region (19) both on the sidewalls of said trench (16) and on said bottom surface of said trench (16).

Claim 16

A semiconductor memory device according to claim 12 wherein said dielectric films (8a) contact said second region (3a) of said cell plate interposed between said two storage nodes (2a).

Claim 17

A semiconductor memory device according to claim 10 wherein said dielectric films (8a) contact said second region (3a) of said cell late interposed between said two storage nodes (2a).

Claim 18

A semiconductor memory device according to claim 9 wherein said dielectric films (8a) contact said second region (3a) of said cell plate interposed between said two storage nodes (2a).