Comparator circuit and analog to digital converter

Claim 2

A comparator circuit for comparing first and second input voltages comprising: first input means for receiving said first input voltage; second input means for receiving said second input voltage; capacitor means having first and second electrodes; first switching means connected between said first input means and said first electrode of said capacitor means; second switching means connected between said second input means and said first electrode of said capacitor means; first inverter means having an input connected to said second electrode of said capacitor means; third switching means connected across said first inverter means; second inverter means having an input conductively connected to the output of said first inverter means; fourth switching means connected across said second inverter means; timing control means connected to said first, second, third and fourth switching means for controlling the switching operations thereof such that said first, third and fourth switching means are turned on whereas said second switching means is turned off at a first timing, and said first, third and fourth switching means are turned off whereas said second switching means is turned on at a second timing later than said first timing.

Claim 3

A comparator circuit according to claim 1 wherein said fourth switching means comprises first transmission gate means.

Claim 4

A comparator circuit according to claim 1 wherein said timing control means signal generating means for generating a first clock signal and a second clock signal inverted with respect to said first clock signal, and said first and second timings are determined by said first and second clock signals.

Claim 5

A comparator circuit according to claim 3 wherein said fourth switching means comprises first transmission gate means and said first transmission gate means comprises: a first field effect device of one conductivity type and having a control electrode; a second field effect device of opposite conductivity having a control electrode and connected parallel to said first field effect device, said first field effect device has said control electrode connected to receive said first clock signal and said second field effect device has its control electrode connected to receive said second clock signal.

Claim 6

A comparator circuit according to claim 1 wherein said inverter means comprises first complementary inverter means and said second inverter means comprises second complementary inverter means.

Claim 7

A comparator circuit according to claim 1 wherein said first switching means comprises second transmission gate means, said second switching means comprises third transmission gate means and said third switching means comprises fourth transmission gate means.

Claim 8

A comparator circuit according to claim 4 wherein said one conductivity type is p-type and said opposite conductivity type is n-type.

Claim 9

An analog to digital converter comprising: a plurality of comparators, each having a first and second inputs; means for generating a plurality of reference voltages connected to said plurality of comparators to apply said reference voltages to said first inputs of said comparators; means connected to said plurality of comparators for applying analog voltage to be converted into digital form to said second inputs of said comparators; encoding means connected to the outputs of said plurality of comparators for encoding the output signals from said comparators into digital signals, each of said plurality of comparators comprising capacitor means having first and second electrodes, first switching means connected between said first electrode of said capacitor means and said first input, second switching means connected between said first electrode of said capacitor means and said second input, first inverter means having its input connected to said second electrodes of said capacitor means, third switching means connected across said first inverter means, second inverter means having its input conductively connected to the output of said first inverter means, fourth switching means connected across said second inverter means, timing control means for controlling the operations of said first, second, third and fourth switching means such that said first, third and fourth switching means are turned on whereas said second switching means is turned off at a first timing, and said first, third and fourth switching means are tuned off while said second switch means is turned on at a second timing later than said first timing.

Claim 10

An analog to digital converter comprising: a plurality of comparators, each having a first and second inputs; means for generating a plurality of reference voltages connected to said plurality of comparators to apply said reference voltages to said first inputs of said comparators; means connected to said plurality of comparators for applying analog voltage to be converted into digital form to said second inputs of said comparators; encoding means connected to the outputs of said plurality of comparators for encoding the output signals from said comparators into digital signals, each of said plurality of comparators comprising capacitor means having first and second electrodes, first switching means connected between said first electrode of said capacitor means and said first input, second switching means connected between said first electrode of said capacitor means and said second input, first inverter means having its input connected to said second electrodes of said capacitor means, third switching means connected across said first inverter means, second inverter means having its input conductively connected to the output of said first inverter means, fourth switching means connected across said second inverter means, timing control means for controlling the operations of said first, second, third and fourth switching means such that said first, third and fourth switching means are turned on whereas said second switching means is turned off at a first timing, and said first, third and fourth switching means are tuned off while said second switch means is turned on at a second timing later than said first timing.

Claim 11

A circuit for amplifying a differential between first and second input signals comprising: an amplifying stage having an input and an output; first switching means connected across said amplifier stage; first means for selectively applying a first signal to said input of said amplifying stage; second means for selectively applying a second input signal to said amplifying stage and for comparing said second input signal with said first input signal and for producing a signal at the output of said amplifying stage indicative of the difference between said second input signal and said first input signal; inverter means having an input conductively connected to the output of said amplifier stage; second switching means connected across said inverter means; timing control means connected to said first and second means for selectively applying input signals to said amplifying stage and to said first and second switching means for controlling the operations thereof such that said first and second switching means are turned on when said first signal is applied to said input of said amplifying stage and are turned off when said second input signal is applied to the input of said amplifying stage.

Claim 12

A circuit for amplifying a differential between first and second input signals comprising: an amplifying stage having an input and an output; first switching means connected across said amplifier stage; first means for selectively applying a first signal to said input of said amplifying stage; second means for selectively applying a second input signal to said amplifying stage and for comparing said second input signal with said first input signal and for producing a signal at the output of said amplifying stage indicative of the difference between said second input signal and said first input signal; inverter means having an input conductively connected to the output of said amplifier stage; second switching means connected across said inverter means; timing control means connected to said first and second means for selectively applying input signals to said amplifying stage and to said first and second switching means for controlling the operations thereof such that said first and second switching means are turned on when said first signal is applied to said input of said amplifying stage and are turned off when said second input signal is applied to the input of said amplifying stage.

Claim 13

A circuit for amplifying a differential between first and second input voltages comprising: an amplifying stage having a capacitive input and an output and first inverter means connected between said capacitive input and said output; first switching means for selectively connecting said first input signal to said capacitive input; second switching means for selectively connecting said second input signal to said capacitive input; third switching means connected across said first inverter means; second inverter means having an input conductively connected to the output of said first inverter means; fourth switching means connected across said second inverter means; timing control means connected to said first, second, third and fourth switching means for controlling the switching operations thereof such that said first, third and fourth switching means are turned on whereas said second switching means is turned off at a first timing, and said first, third and fourth switching means are turned off whereas said second switching means is turned on at a second timing later than said first timing.

Claim 14

A circuit for amplifying a differential between first and second input voltages comprising: an amplifying stage having a capacitive input and an output and first inverter means connected between said capacitive input and said output; first switching means for selectively connecting said first input signal to said capacitive input; second switching means for selectively connecting said second input signal to said capacitive input; third switching means connected across said first inverter means; second inverter means having an input conductively connected to the output of said first inverter means; fourth switching means connected across said second inverter means; timing control means connected to said first, second, third and fourth switching means for controlling the switching operations thereof such that said first, third and fourth switching means are turned on whereas said second switching means is turned off at a first timing, and said first, third and fourth switching means are turned off whereas said second switching means is turned on at a second timing later than said first timing.

Claim 15

A comparator circuit for comparing first and second voltages comprising: a first input node for receiving said first voltage, first switching means connected between said first input node and a first connecting node, a second input node for receiving said second voltage, second switching means connected between said second input node and said first connecting node, capacitor means connected between said first connecting node and a second connecting node, first inverter means having an input node and an output node, said inverter means having the input node connected to said second connecting node, third switching means connected between the input node and the output node of said first inverter means, second inverter means having an input node and an output node, said second inverter means having the input node directly connected to the output node of said first inverter means, and fourth switching means connected between the input node and the output node of said second inverter means, said fourth switching means being in a conductive state when said third switching means is in a conductive state, said fourth switching means being in a non-conductive state when said third switching means is in a non-conductive state.

Claim 16

A comparator circuit for comparing first and second voltages comprising: a first input node for receiving said first voltage, first switching means connected between said first input node and a first connecting node, a second input node for receiving said second voltage, second switching means connected between said second input node and said first connecting node, capacitor means connected between said first connecting node and a second connecting node, first inverter means having an input node and an output node, said inverter means having the input node connected to said second connecting node, third switching means connected between the input node and the output node of said first inverter means, second inverter means having an input node and an output node, said second inverter means having the input node directly connected to the output node of said first inverter means, and fourth switching means connected between the input node and the output node of said second inverter means, said fourth switching means being in a conductive state when said third switching means is in a conductive state, said fourth switching means being in a non-conductive state when said third switching means is in a non-conductive state.

Claim 17

A comparator circuit according to claim 11, wherein said first voltage includes a reference voltage, and said second voltage includes a signal voltage to be compared with said reference voltage.

Claim 18

A comparator circuit according to claim 11, said third switching means shunting voltages at the input node and the output node of said first inverter means, said fourth switching means shunting voltages at the input node and the output node of said second inverter means.