Voltage regulator with reduced semiconductor power dissipation

Claim 1

A linear, series pass voltage regulator including an input for receiving an unregulated first DC voltage and including an output for supplying a variable load current at a regulated second DC voltage having a predetermined magnitude, said voltage regulator comprising: a. a variable impedance output stage electrically connected between the input and the output for carrying the load current; and b. control circuitry electrically connected to the voltage regulator input and to the output stage for comparing the second DC voltage to a reference voltage and for producing a control signal for controlling the impedance of the output stage to effect maintenance of the second DC voltage at the predetermined magnitude despite variations of the first DC voltage and the load current; characterized in that the output stage comprises: (1) a first impedance comprising a series combination of a resistor and a first semiconductor device output impedance electrically connected between the input and the output of the regulator, said first semiconductor device having an input for receiving said control signal to effect variation of the device output impedance; (2) a second impedance comprising a series combination of a second semiconductor device output impedance and voltage-dropping semiconductor means electrically connected between the input and the output of the regulator, said second semiconductor device having an input for receiving said control signal to effect variation of the device output impedance, said input of said second semiconductor device being electrically connected to the control circuitry for receiving the control signal; and (3) resistive coupling means electrically connecting a junction between the voltage-dropping semiconductor junction means and the output impedance of the second semiconductor device to the input of the first semiconductor device for coupling the control signal to said input of said first semiconductor device, said control signal effecting, in sequence, a gradual decrease in the first impedance from a high value to a low value as the load current increases to a predetermined magnitude, while the second impedance remains at a value which is much higher than the value of the first impedance, followed by a gradual decrease in the second impedance from said higher value as the load current increases above said predetermined magnitude, while the first impedance remains at said low value.