US5008852A
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Parallel accessible memory device
Assignee: Toshiba Corp
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Filing: 1988-03-30
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Granted: 1991-04-16
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Expires: 2008-03-30
Abstract
Abstract A parallel-accessible memory device of one or multiple dimensions has submemories for the respective dimensions. Each of the submemories has a capacity provided by dividing the total memory capacity by positive integers given for the respective dimensions. The memory device comprises an address converting section for generating addresses of the submemories of the respective dimensions according to dimensional addresses; a data rearranging section for rearranging input and output data of the submemories in a required order, the input and output data being specified by the submemory addresses from the address converting section; and a write controlling section for selectively renewing data in a region of the submemories of the respective dimensions.
Inventors
- 👤 Hiroshi Mizoguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:06
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/60; G06F; G06F12/00; G06F12/02; G06F12/0207
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
250 words
A parallel accessible M-dimensional memory device, comprising: N i column submemories for i-th dimension (i=1, . . . , M) where N i is a positive integer, each one of the N i column submemories having 1/N i ×N 2 ×. . . ×N n capacity of a total memory capacity of the device, each one of the N i column submemories having addresses addressed by an integer submemory address S j =0, 1, 2, . . . (j-0, 1, . . . , N i -1) labeling rows within each column submemory, the addresses of the N i column submemories being also addressed by an M-dimensional integer input address X i =0, 1, 2, . . . (i=1 , . . . , M) labeling the addresses of all of the N i column submemories collectively, and where (j+1)-th one of the N i column submemories stores (j+1+nN i )-th data for i-th dimension, (n=0, 1, . . . ): address converting means for obtaining N i submemory addresses S j for N i data to be parallel accessed, for the M-dimensional input addresses X i supplied externally; and data rearranging means for rearranging the N i data read out from the N i submemory addresses S j of the N i submemories obtained by the address converting means, in accordance with the M-dimensional input address X i , such that the N i data are arranged in an order labeled by the M-dimensional input address X i .
Claim 2
Dependent Claim
250 words
A parallel accessible M-dimensional memory device, comprising: N i column submemories for i-th dimension (i=1, . . . , M) where N i is a positive integer, each one of the N i column submemories having 1/N i ×N 2 ×. . . ×N n capacity of a total memory capacity of the device, each one of the N i column submemories having addresses addressed by an integer submemory address S j =0, 1, 2, . . . (j-0, 1, . . . , N i -1) labeling rows within each column submemory, the addresses of the N i column submemories being also addressed by an M-dimensional integer input address X i =0, 1, 2, . . . (i=1 , . . . , M) labeling the addresses of all of the N i column submemories collectively, and where (j+1)-th one of the N i column submemories stores (j+1+nN i )-th data for i-th dimension, (n=0, 1, . . . ): address converting means for obtaining N i submemory addresses S j for N i data to be parallel accessed, for the M-dimensional input addresses X i supplied externally; and data rearranging means for rearranging the N i data read out from the N i submemory addresses S j of the N i submemories obtained by the address converting means, in accordance with the M-dimensional input address X i , such that the N i data are arranged in an order labeled by the M-dimensional input address X i .
Claim 3
Dependent Claim
35 words
The device of claim 1, wherein the address converting means obtains the N i submemory addresses S j from the M-dimensional input address X i according to a formula: S.sub.j =(X.sub.i +N.sub.i -1-j) div N.sub.i
Claim 4
Dependent Claim
38 words
The device of claim 2, wherein the address converting means further comprises: adder means for calculating A=(X i +N i -1-j); and divider means for calculating A/N i in accordance with the A calculated by the adder means.
Claim 5
Dependent Claim
45 words
The device of claim 3, wherein N i =2 p where p is a positive integer, and wherein the divider means receives the A in binary expression and calculates the A/N i as a number obtained by removing p least significant bits from the A.
Claim 6
Dependent Claim
114 words
The device of claim 1, wherein the data rearranging means includes N i bidirectional data selector means, provided in correspondence with the N i column submemories, for rearranging the N i data, where (j-1)-th one of the N i bidirectional data selector means receives all of the N i data, obtains a series of the N i data in which the N i data are arranged in an order labeled by the M-dimensional input address X i and then cyclically permutated such that the series starts from the (j+1)-th one of the N i data, and output one of the N i data selected in accordance with the M-dimensional input address X i .
Claim 7
Dependent Claim
70 words
The device of claim 5, wherein N i =2 p where p is a positive integer, and wherein the (j+1)-th one of the N i bidirectional data selector means selects one of the N 1 data to be outputted by selecting q-th data in the series of the N i data, where q is a number specified by p least significant bits of the M-dimensional input address X i .
Claim 8
Dependent Claim
71 words
The device of claim 1, further comprising write controlling means for selectively allowing a part of the N 1 data to be overwritten by new data, by providing a write control signal to each one of the N i column submemories, the write control signal indicating whether one of the N i data read out from each one of the N i column submemories belongs to the part to be overwritten.
Claim 9
Dependent Claim
122 words
The device of claim 7, wherein the write controlling means further comprises: masking register means for providing indication for the part of the N i data to be overwritten in an arrangement of the N i data obtained by the data rearranging means; additional data rearranging means for rearranging the indication from the masking register means from the arrangement of the N i data obtaining by the data rearranging means into an arrangement of the N i data stored in the N i column submemories; and AND gate means for producing the write control signal by taking logical AND product of the indication from the masking register means as rearranged by the additional data rearranging means and an externally supplied write command.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-15 | 1994-10-15 | 1995-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-15 | 1998-10-15 | 1999-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-15 | 2002-10-15 | 2003-04-16 | $7700.00 | Window Closed / Lapsed |