Method and apparatus for generating an auxiliary timing signal in the horizontal blanking interval of a video signal

Claim 3

The method of claim 1, wherein said memory is programmed so that said clock frequency is an even multiple of said reference frequency.

Claim 4

The method of claim 1, wherein said memory is so programmed that said clock frequency is the 8-fold multiple of said reference frequency.

Claim 5

The method of claim 1, wherein said video signal is a digital video signal and wherein said less significant bits from said first memory means are inserted in the digital data stream of said video signal and thereafter said video signal data stream is converted from digital-to-analog form in a converter to which said most significant bit of said second memory means is supplied as the most significant bit for said digital-to-analog conversion, and wherein the resulting analog video signal containing said auxiliary signal is filtered and clamped after the digital-to-analog conversion.

Claim 6

The method of claim 4, wherein said filtering includes a Tschebyscheff filter, having a linear frequency characteristic rising to a frequency greater than twice said reference frequency, and at least one following stage for compensation of the damping effect of digital-to-analog and low-pass filtering steps.

Claim 9

The method of claim 6, wherein prior to the step of additive combination for insertion of said auxiliary signal into said video signal, said auxiliary signal and, likewise, said video signal are clamped to a predetermined d.c. level by a clamping pulse provided during each said horizontal blanking interval.

Claim 10

The method claim 6, wherein said memory is programmed so that said oscillations of said reference frequency will have a time course which includes precompensation for damping effects of said low-pass filtering and of said conversion from digital to analog form.

Claim 11

The method of claim 6, wherein said low-pass filtering is performed with a Bessel low-pass filter having a cut-off frequency of about twice said reference frequency.

Claim 12

Apparatus for inserting an auxiliary signal into the horizontal blanking intervals of an analog video signal, said auxiliary signal including reference oscillations at a frequency locked to a clock frequency itself locked to the horizontal scan frequency, comprising: means (3) for deriving a signal (CLK) of said clock frequency from said horizontal scan frequency of said video signal; means (6, 7, 8, 10) activated by said clock frequency signal (CLK) only during said blanking intervals, responsive to said clock frequency signal (CLK), a horizontal blanking interval signal (A H ) and a vertical synchronizing signal (2V) both derived from said video signal, for producing a sequence of address signals in each of said horizontal blanking intervals; read only memory means (9) responsive to said address signals for generating a digital signal representative of said auxiliary signal; means (11) for converting said digital signal representative of said auxiliary signal into an analog signal; means (12) for low-pass filtering said analog signal to produce said auxiliary signal, and means (15) for inserting said auxiliary signal into the horizontal blanking intervals of said analog video signal.

Claim 13

Apparatus for inserting an auxiliary signal into the horizontal blanking intervals of an analog video signal, said auxiliary signal including reference oscillations at a frequency locked to a clock frequency itself locked to the horizontal scan frequency, comprising: means (3) for deriving a signal (CLK) of said clock frequency from said horizontal scan frequency of said video signal; means (6, 7, 8, 10) activated by said clock frequency signal (CLK) only during said blanking intervals, responsive to said clock frequency signal (CLK), a horizontal blanking interval signal (A H ) and a vertical synchronizing signal (2V) both derived from said video signal, for producing a sequence of address signals in each of said horizontal blanking intervals; read only memory means (9) responsive to said address signals for generating a digital signal representative of said auxiliary signal; means (11) for converting said digital signal representative of said auxiliary signal into an analog signal; means (12) for low-pass filtering said analog signal to produce said auxiliary signal, and means (15) for inserting said auxiliary signal into the horizontal blanking intervals of said analog video signal.

Claim 14

The apparatus of claim 10, wherein said means for inserting said auxiliary signal into the horizontal blanking intervals of said analog video signal comprise signal addition means having a first input for said analog video signal and a second input for said auxiliary signal, a first clamping stage having an input for said analog video signal and an output connected with said input of said addition means and a second clamping stage having an input for receiving said auxiliary signal and an output connected to said second input of said addition means, and means for providing a clamping pulse (H C ) of horizontal scan frequency and for applying the same to said first and second clamping means.

Claim 15

Apparatus for inserting an auxiliary signal into the horizontal blanking intervals of a digital video signal, said auxiliary signal including reference oscillations at a frequency locked to a clock frequency itself locked to the horizontal scan frequency of said video signal comprising: means (103) for deriving a signal (CLK) of said clock frequency from said horizontal scan frequency of said video signal; means (106, 107, 108, 110) activated by said clock frequency signal (CLK) only during said blanking intervals, responsive to said clock frequency signal (CLK), a horizontal blanking interval signal (A H ) and a vertical synchronizing signal (2V) both derived from said video signal, for producing a sequence of address signals in each of said horizontal blanking intervals; read-only memory means (109) responsive to said address signals generating a digital signal representative of said auxiliary signal, said memory means including a first memory portion for producing 8 less significant bits defining a portion of said auxiliary signal consisting of said reference oscillations and a pedestal therefor and a second memory portion providing a most significant bit output for defining the remainder of said auxiliary signal, including a horizontal synchronizing signal; digital-to-analog conversion means having an analog output, eight less significant bit inputs connected both to a source of said digital video signal and to said less significant bit outputs of said first memory portion and a most significant bit input connected to said most significant bit output of said second memory portion; means (115, 116) for filtering said analog output of said conversion means, and means for clamping the output of said filtering means for fixing the d.c. level of said output and including means for providing horizontal frequency clamping pulses, derived from said digital video signal, for controlling said clamping means.

Claim 16

Apparatus for inserting an auxiliary signal into the horizontal blanking intervals of a digital video signal, said auxiliary signal including reference oscillations at a frequency locked to a clock frequency itself locked to the horizontal scan frequency of said video signal comprising: means (103) for deriving a signal (CLK) of said clock frequency from said horizontal scan frequency of said video signal; means (106, 107, 108, 110) activated by said clock frequency signal (CLK) only during said blanking intervals, responsive to said clock frequency signal (CLK), a horizontal blanking interval signal (A H ) and a vertical synchronizing signal (2V) both derived from said video signal, for producing a sequence of address signals in each of said horizontal blanking intervals; read-only memory means (109) responsive to said address signals generating a digital signal representative of said auxiliary signal, said memory means including a first memory portion for producing 8 less significant bits defining a portion of said auxiliary signal consisting of said reference oscillations and a pedestal therefor and a second memory portion providing a most significant bit output for defining the remainder of said auxiliary signal, including a horizontal synchronizing signal; digital-to-analog conversion means having an analog output, eight less significant bit inputs connected both to a source of said digital video signal and to said less significant bit outputs of said first memory portion and a most significant bit input connected to said most significant bit output of said second memory portion; means (115, 116) for filtering said analog output of said conversion means, and means for clamping the output of said filtering means for fixing the d.c. level of said output and including means for providing horizontal frequency clamping pulses, derived from said digital video signal, for controlling said clamping means.

Claim 17

The apparatus of claim 12, wherein the outputs of said read-only memory means (109, 110) pass through a first register interposed between said memory means and digital-to-analog converter and a second register is provided which is interposed between said source of said digital video signal and said less significant inputs of said digital to analog conversion means, both said first and second registers being connected for being clocked by said clock frequency signal (CLK), said first register being enabled during said horizontal blanking intervals and said second register being enabled in the absence of said horizontal blanking intervals respectively by means for supplying a horizontal blanking signal inversely applied to said first register and directly applied to said second register.