US5008720A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with stepped well
Assignee: Mitsubishi Electric Corp
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Filing: 1990-01-02
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Granted: 1991-04-16
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Expires: 2010-01-02
Abstract
Abstract A semiconductor device comprises a first conductivity type semiconductor layer and a second conductivity type well region which is formed on the semiconductor layer. The well region includes a first semiconductor region of a first depth and a second semiconductor region of a second depth deeper than the first depth which is provided in the central portion of the first semiconductor region. The ratio of the first depth to the second depth is settled in a range from 0.85 to 0.95 in order to increase the breakdown voltage of the semiconductor device.
Inventors
- 👤 Akio Uenishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/035; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D62/00; H10D62/10; H10D62/124; H10D62/125; H10D62/17; H10D62/393; H10D62/102; H10D62/103; H10D62/105; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10D64/2527; H10D64/256
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
78 words
A semiconductor device comprising: a first conductivity type semiconductor layer; and a second conductivity type well region formed on said semiconductor layer; said well region having a first semiconductor region of a first depth and a second semiconductor region of a second depth deeper than said first depth, said second semiconductor region being provided in a central portion of said first semiconductor region, a ratio of said first depth to said second depth ranging from 0.85 to 0.95.
Claim 2
Dependent Claim
78 words
A semiconductor device comprising: a first conductivity type semiconductor layer; and a second conductivity type well region formed on said semiconductor layer; said well region having a first semiconductor region of a first depth and a second semiconductor region of a second depth deeper than said first depth, said second semiconductor region being provided in a central portion of said first semiconductor region, a ratio of said first depth to said second depth ranging from 0.85 to 0.95.
Claim 3
Dependent Claim
28 words
A semiconductor device in accordance with claim 1, wherein a width of said first semiconductor region is less than or equal to 1.5 times of said first depth.
Claim 4
Dependent Claim
36 words
A semiconductor device in accordance with claim 1, wherein said well region includes a plurality of well regions, and a distance between said plurality of well regions is greater than two times of said first depth.
Claim 5
Dependent Claim
82 words
A semiconductor device comprising: a first conductivity type semiconductor layer; a second conductivity type well region formed on said semiconductor layer; and a second conductivity type guard ring formed on said semiconductor layer around said well region, said guard ring having a multistep structure in which an outer step of said multistep structure is shallower in depth than an inner step of said multistep structure and a ratio of a depth between adjacent steps of said multistep structure is 0.85 to 0.95.
Claim 6
Dependent Claim
82 words
A semiconductor device comprising: a first conductivity type semiconductor layer; a second conductivity type well region formed on said semiconductor layer; and a second conductivity type guard ring formed on said semiconductor layer around said well region, said guard ring having a multistep structure in which an outer step of said multistep structure is shallower in depth than an inner step of said multistep structure and a ratio of a depth between adjacent steps of said multistep structure is 0.85 to 0.95.
Claim 7
Dependent Claim
148 words
A semiconductor device comprising: a first conductivity type semiconductor layer having first and second major surface; a second conductivity type well region selectively formed in said first major surface of said semiconductor layer; a first conductivity type semiconductor region selectively formed in a surface of said well region; an insulation layer formed on a portion of a surface of said well region between surfaces of said semiconductor layer and said semiconductor region; a control electrode formed on said insulation layer; a first main electrode formed on said semiconductor region; and a second main electrode formed on said second major surface of said semiconductor layer, said well region having a steped configuration composed of a peripheral portion of a first depth and a central portion of a second depth deeper than said first depth, a ratio of said first depth to said second depth ranging from 0.85 to 0.95.
Claim 8
Dependent Claim
148 words
A semiconductor device comprising: a first conductivity type semiconductor layer having first and second major surface; a second conductivity type well region selectively formed in said first major surface of said semiconductor layer; a first conductivity type semiconductor region selectively formed in a surface of said well region; an insulation layer formed on a portion of a surface of said well region between surfaces of said semiconductor layer and said semiconductor region; a control electrode formed on said insulation layer; a first main electrode formed on said semiconductor region; and a second main electrode formed on said second major surface of said semiconductor layer, said well region having a steped configuration composed of a peripheral portion of a first depth and a central portion of a second depth deeper than said first depth, a ratio of said first depth to said second depth ranging from 0.85 to 0.95.
Claim 9
Dependent Claim
165 words
A semiconductor device comprising: a first conductivity type first semiconductor layer having first and second major surface; a second conductivity type well region selectively formed in said first major surface of said first semiconductor layer; a first conductivity type semiconductor region selectively formed in a surface of said well region; a second conductivity type second semiconductor layer formed on said second major surface of said first semiconductor layer; an insulation layer formed on a portion of a surface of said well region between surfaces of said first semiconductor layer and said semiconductor region; a control electrode formed on said insulation layer; a first main electrode formed on said semiconductor region; and a second main electrode formed on said second semiconductor layer, said well region having a steped configuration composed of a peripheral portion of a first depth and a central portion of a second depth deeper than said first depth, a ratio of said first depth to said second depth ranging from 0.85 to 0.95.
Claim 10
Dependent Claim
165 words
A semiconductor device comprising: a first conductivity type first semiconductor layer having first and second major surface; a second conductivity type well region selectively formed in said first major surface of said first semiconductor layer; a first conductivity type semiconductor region selectively formed in a surface of said well region; a second conductivity type second semiconductor layer formed on said second major surface of said first semiconductor layer; an insulation layer formed on a portion of a surface of said well region between surfaces of said first semiconductor layer and said semiconductor region; a control electrode formed on said insulation layer; a first main electrode formed on said semiconductor region; and a second main electrode formed on said second semiconductor layer, said well region having a steped configuration composed of a peripheral portion of a first depth and a central portion of a second depth deeper than said first depth, a ratio of said first depth to said second depth ranging from 0.85 to 0.95.
References Cited (Backward Citations)
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Cited
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