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US5008632A Expired / Lapsed US ⏱️ 0.0 years remaining

Temperature compensated feedback circuit for setting and stabilizing amplifier DC bias points

Assignee: International Business Machines Corp
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Filing: 1989-10-31
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Granted: 1991-04-16
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Expires: 2009-10-31
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Abstract

Abstract Described is an improved differential amplifier arrangement with a temperature compensated feedback circuit which sets and stabilizes the DC bias point of the amplifier. The circuit averages the two outputs of the amplifier and generates a DC voltage which is compared with a reference voltage to generate a control signal which is amplified and is used to control the bias point of the amplifier.

Inventors

  • 👤 Philip H. Sutterlin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 08:00
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F3/00; H03F3/45; H03F3/45071; H03F3/45479; H03F3/45484; H03F3/45488; H03F3/45493; H03F3/45502; H03F2203/00; H03F2203/45; H03F2203/45008; H03F2203/45074; H03F2203/45076; H03F2203/45082; H03F2203/45202; H03F2203/45212; H03F2203/45266; H03F2203/45392; H03F2203/45418; H03F2203/45424; H03F2203/45466; H03F2203/45476; H03F2203/45702

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 157 words
An improved amplifier comprising: a differential amplifier stage having differential input devices (Q 1 , Q 2 ) with a pair of differential input terminals for receiving an input signal, a pair of output terminals, interconnected collector terminals, and interconnected emitter terminals; a buffer stage, coupled to the pair of output terminals; a first circuit means connected in the interconnected collector terminals, said first circuit means averaging signals in said interconnected collector terminals and generating a single-ended signal representative of a DC component in said signals; a second circuit means for generating a reference signal (Vref); a third circuit means to compensate for temperature and process variations caused by said buffer stage, coupled to the second circuit means; an error amplifier coupled to the third circuit means for comparing Vref with the single-ended signal to generate a bias current signal which directly flows through (Q1, Q2) to set the DC operating point of said differential amplifier stage.
Claim 2
Dependent Claim 157 words
An improved amplifier comprising: a differential amplifier stage having differential input devices (Q 1 , Q 2 ) with a pair of differential input terminals for receiving an input signal, a pair of output terminals, interconnected collector terminals, and interconnected emitter terminals; a buffer stage, coupled to the pair of output terminals; a first circuit means connected in the interconnected collector terminals, said first circuit means averaging signals in said interconnected collector terminals and generating a single-ended signal representative of a DC component in said signals; a second circuit means for generating a reference signal (Vref); a third circuit means to compensate for temperature and process variations caused by said buffer stage, coupled to the second circuit means; an error amplifier coupled to the third circuit means for comparing Vref with the single-ended signal to generate a bias current signal which directly flows through (Q1, Q2) to set the DC operating point of said differential amplifier stage.

References Cited (Backward Citations)

US3444472A Cited
US4105942A Cited
US4616189A Cited
US4701719A Cited
US4720686A Cited
US4904953A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-04-15 1994-10-15 1995-04-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-04-15 1998-10-15 1999-04-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-04-15 2002-10-15 2003-04-16 $7700.00 Window Closed / Lapsed

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