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US5006913A Expired / Lapsed US ⏱️ 0.0 years remaining

Stacked type semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1989-11-02
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Granted: 1991-04-09
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Expires: 2009-11-02
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Abstract

Abstract A field effect transistor is formed as a first semiconductor element on a main surface of a first semiconductor layer (1). An interlayer insulating film (10) constituted by a first insulating layer (101) and a second insulating layer (102) is formed on the first semiconductor element. The first insulating layer (101) is formed of a BPSG film having a glass transition point no higher than 750° C. The second insulating layer (102) is formed of a silicon oxide film having a glass transition point higher than 750° C. and a thickness no less than 2000 Å and no more than 1 μm formed on the first insulating layer (101). A second semiconductor layer (11) is formed on the second insulating layer (102) of the interlayer insulating film (10). The second semiconductor layer (11) is formed to be an island, with the peripheral portions isolated. A field effect transistor as a second semiconductor element is formed in the second semiconductor layer (11). The first insulating layer (101) suppresses stress remained in the second semiconductor layer (11) derived from a difference between coefficient of thermal expansion of the second semiconductor layer (11) and the interlayer insulating film (10). The second insulating layer (102) suppresses lateral distortion generated in the semiconductor layer (11). The characteristics of the second semiconductor element can be improved.

Inventors

  • 👤 Kazuyuki Sugahara
  • 👤 Shigeru Kusunoki
  • 👤 Takashi Ipposhi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 22:33
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 118 words
A stacked type semiconductor device, comprising: a first semiconductor layer having a main surface on which a first semiconductor element is formed; an interlayer insulating film having a first insulating layer having a glass transition point of no higher than 750° C. formed on said first semiconductor element and a second insulating layer having a glass transition point higher than 750° C. and a thickness no less than 2000Å and no more than 1 μm formed on said first insulating layer; and a second semiconductor layer formed on said second insulating layer of said interlayer insulating film with peripheral portions isolated to have an island-like shape, having a main surface on which a second semiconductor element is formed.
Claim 2
Dependent Claim 118 words
A stacked type semiconductor device, comprising: a first semiconductor layer having a main surface on which a first semiconductor element is formed; an interlayer insulating film having a first insulating layer having a glass transition point of no higher than 750° C. formed on said first semiconductor element and a second insulating layer having a glass transition point higher than 750° C. and a thickness no less than 2000Å and no more than 1 μm formed on said first insulating layer; and a second semiconductor layer formed on said second insulating layer of said interlayer insulating film with peripheral portions isolated to have an island-like shape, having a main surface on which a second semiconductor element is formed.
Claim 3
Dependent Claim 34 words
A stacked type semiconductor device according to claim 1, wherein said first insulating layer comprises a silicon oxide film doped with boron and phosphorous, and said second insulating layer comprises a silicon oxide film.
Claim 4
Dependent Claim 81 words
A stacked type semiconductor device according to claim 1, wherein said first semiconductor element comprises a field effect transistor having impurity regions of a second conductivity type formed spaced apart from each other in said first semiconductor layer so as to define a channel region having a portion of the main surface of said first semiconductor layer of a first conductivity type as a channel surface, and a gate electrode formed on said channel surface with an insulating film interposed therebetween.
Claim 5
Dependent Claim 81 words
A stacked type semiconductor device according to claim 3, wherein said second semiconductor element comprises a field effect transistor having impurity regions of a first conductivity type formed spaced apart from each other in said second semiconductor layer so as to define a channel region having a portion of the main surface of said second semiconductor layer of a second conductivity type as a channel surface, and a gate electrode formed on said channel surface with an insulating film interposed therebetween.

References Cited (Backward Citations)

JPS587861A Cited
FR2595165A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-04-08 1994-10-08 1995-04-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-04-08 1998-10-08 1999-04-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-04-08 2002-10-08 2003-04-09 $7700.00 Window Closed / Lapsed

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