Hysteresis insensitive analog to digital converter system using a coarse comparator and a fine comparator

Claim 2

A circuit for converting an analog signal into a digital value comprising a plurality of bits, the circuit comprising: a capacitor array comprising a capacitor corresponding to each bit in the digital value; a top plate coupling together a first node of each capacitor in said array; capacitor control switching means operable to selectively couple a second node of said capacitors to a reference signal and said analog signal; a coarse comparator circuit having an input and an output and operable to generate a predetermined number of most significant bits of the plurality of bits representing said digital value; a fine comparator circuit having an input and an output and operable to generate the remaining bits of said plurality of bits representing said digital value such that the generation of the least significant bits of the digital value will not be affected by hystersis effects of large voltages at the inputs to said comparator circuit; a course switch operable to selectively couple said top plate to said input or said course comparator circuit; and a fine switch operable to selectively couple said top plate to said input of said fine comparator circuit.

Claim 3

The circuit of claim 1 and further comprising: first sequential circuitry coupled to selected ones of said capacitor control switches corresponding to said capacitors corresponding to said predetermined number of most significant bits, said first sequential circuitry operable to sequentially couple said predetermined number of said capacitors to said reference voltage; and coarse storage circuitry coupled to said output of said coarse comparator circuit and operable to log a first set of results of sequential comparisons of a voltage on said top plate to a threshold voltage associated with said coarse comparator circuit, said coarse comparator circuit operable to make said sequential comparisons as each of said capacitors associated with said predetermined number of the most significant bits of the digital value is sequentially coupled to said reference voltage, said first set of results comprising said predetermined number of the most significant bits of the digital value.

Claim 4

The circuit of claim 2 and further comprising: second sequential circuitry coupled to selected ones of said capacitor control switches corresponding to said capacitors corresponding to the remaining bits of the digital value, said second sequential circuitry operable to sequentially couple said remaining capacitors to said reference voltage; and fine storage circuitry coupled to said output of said fine comparator circuit and operable to log a second set of results of sequential comparisons of a voltage on said top plate to a threshold voltage associated with said fine comparator circuit, said fine comparator circuit operable to make said sequential comparisons as each of said capacitors associated with the remaining bits of the digital value is sequentially coupled to said reference voltage, said second set of results comprising the remaining bits of the digital value.

Claim 5

A circuit for converting an analog voltage signal into a digital value comprising a plurality of bits, the circuit comprising: a coarse comparator circuit having an input and an output and operable to generate a predetermined number of the most significant of the bits; a fine comparator circuit having an input and an output and operable to generate the remaining bits of the plurality such that the generation of the least significant bits of the digital value will not be affected by hysteresis effects of large voltages at said inputs to said comparator circuit; a capacitor array comprising a capacitor corresponding to each bit in the digital value; a top plate coupling together a first node of each of said capacitors; a capacitor control switch associated with each of said capacitors and operable to selectively couple a second node of each of said capacitors to a reference voltage, a predetermined voltage level and the analog voltage signal; circuitry coupled to each of said capacitor control switches for sequentially coupling said second node of each of said capacitors to said reference voltage; circuitry for selectively coupling said top plate to said input of said coarse comparator circuit; coarse storage circuitry coupled to said output of said coarse comparator circuit and operable to log a first set of results of sequential comparisons of a voltage on said top plate to a threshold voltage associated with said coarse comparator circuit, said coarse comparator circuitry operable to make said sequential comparisons as each of said capacitors associated with said predetermined number of the most significant bits of the digital value is sequentially coupled to said reference voltage, said first set of results comprising said predetermined number of the most significant bits of the digital value; circuitry for selectively coupling said top plate to said input of said fine comparator circuit; fine storage circuitry coupled to said output of said fine comparator circuit and operable to log a second set of results of sequential comparisons of a voltage on said top plate to a threshold voltage associated with said fine comparator circuit, said fine comparator circuit operable to make said sequential comparisons as each of said capacitors associated with the remaining bits of the digital value is sequentially coupled to said reference voltage, said second set of results comprising the remaining bits of the digital value; circuitry for generating a first value for the least significant bit of the predetermined number of bits using the bits generated by the coarse comparator circuit; circuitry for generating a second value for the least significantly bit of the predetermined number of bits using a value corresponding to the bits generated by said coarse comparator circuit with one added to the least significant bit position, the first and second values determining the accurate value of the least significant bit of the bits generated by the course comparator circuit; and circuitry for selectively correcting the digital value responsive to selected values for said first and second values.

Claim 6

A circuit for converting an analog voltage signal into a digital value comprising a plurality of bits, the circuit comprising: a coarse comparator circuit having an input and an output and operable to generate a predetermined number of the most significant of the bits; a fine comparator circuit having an input and an output and operable to generate the remaining bits of the plurality such that the generation of the least significant bits of the digital value will not be affected by hysteresis effects of large voltages at said inputs to said comparator circuit; a capacitor array comprising a capacitor corresponding to each bit in the digital value; a top plate coupling together a first node of each of said capacitors; a capacitor control switch associated with each of said capacitors and operable to selectively couple a second node of each of said capacitors to a reference voltage, a predetermined voltage level and the analog voltage signal; circuitry coupled to each of said capacitor control switches for sequentially coupling said second node of each of said capacitors to said reference voltage; circuitry for selectively coupling said top plate to said input of said coarse comparator circuit; coarse storage circuitry coupled to said output of said coarse comparator circuit and operable to log a first set of results of sequential comparisons of a voltage on said top plate to a threshold voltage associated with said coarse comparator circuit, said coarse comparator circuitry operable to make said sequential comparisons as each of said capacitors associated with said predetermined number of the most significant bits of the digital value is sequentially coupled to said reference voltage, said first set of results comprising said predetermined number of the most significant bits of the digital value; circuitry for selectively coupling said top plate to said input of said fine comparator circuit; fine storage circuitry coupled to said output of said fine comparator circuit and operable to log a second set of results of sequential comparisons of a voltage on said top plate to a threshold voltage associated with said fine comparator circuit, said fine comparator circuit operable to make said sequential comparisons as each of said capacitors associated with the remaining bits of the digital value is sequentially coupled to said reference voltage, said second set of results comprising the remaining bits of the digital value; circuitry for generating a first value for the least significant bit of the predetermined number of bits using the bits generated by the coarse comparator circuit; circuitry for generating a second value for the least significantly bit of the predetermined number of bits using a value corresponding to the bits generated by said coarse comparator circuit with one added to the least significant bit position, the first and second values determining the accurate value of the least significant bit of the bits generated by the course comparator circuit; and circuitry for selectively correcting the digital value responsive to selected values for said first and second values.

Claim 9

A circuit for converting an analog signal into a digital value comprising a plurality of bits, the circuit comprising: a coarse comparator circuit having an input and an output and operable to generate a predetermined number of most significant bits of the plurality; a fine comparator circuit having an input and an output and operable to generate the remaining bits of the plurality such that the generation of the least significant bits of the digital value will not be affected by hysteresis effects of large voltages at the inputs to said comparator circuit; circuitry for generating a first value for the least significant bit of the predetermined number of bits using the bits generated by the coarse comparator circuit; circuitry for generating a second value for the least significant bit of the predetermined number of bits using a value corresponding to the bits generated by the coarse comparator with one added in the least significant bit position, the first and second values determining the accurate value of the least significant bit of the bits generated by the coarse comparator circuit; and circuitry for selectively correcting the digital value responsive to said circuitry for checking.

Claim 10

A circuit for converting an analog signal into a digital value comprising a plurality of bits, the circuit comprising: a coarse comparator circuit having an input and an output and operable to generate a predetermined number of most significant bits of the plurality; a fine comparator circuit having an input and an output and operable to generate the remaining bits of the plurality such that the generation of the least significant bits of the digital value will not be affected by hysteresis effects of large voltages at the inputs to said comparator circuit; circuitry for generating a first value for the least significant bit of the predetermined number of bits using the bits generated by the coarse comparator circuit; circuitry for generating a second value for the least significant bit of the predetermined number of bits using a value corresponding to the bits generated by the coarse comparator with one added in the least significant bit position, the first and second values determining the accurate value of the least significant bit of the bits generated by the coarse comparator circuit; and circuitry for selectively correcting the digital value responsive to said circuitry for checking.

Claim 11

A circuit for converting an analog signal into a digital value comprising a plurality of bits, the circuit comprising: a coarse comparator circuit having an input and an output and operable to generate a predetermined number of most significant bits of the plurality; a fine comparator circuit having an input and an output and operable to generate the remaining bits of the plurality such that the generation of the least significant bits of the digital value will not be affected by hysteresis effects of large voltages at the inputs to said comparator circuit; a capacitor array comprising a capacitor corresponding to each bit in the digital value; a top plate coupling together a first node of each of said capacitors; a coarse switch operable to selectively couple said top plate to said input of said coarse comparator circuit; and a fine switch operable to selectively couple said top plate to said input of said fine comparator circuit.

Claim 12

A circuit for converting an analog signal into a digital value comprising a plurality of bits, the circuit comprising: a coarse comparator circuit having an input and an output and operable to generate a predetermined number of most significant bits of the plurality; a fine comparator circuit having an input and an output and operable to generate the remaining bits of the plurality such that the generation of the least significant bits of the digital value will not be affected by hysteresis effects of large voltages at the inputs to said comparator circuit; a capacitor array comprising a capacitor corresponding to each bit in the digital value; a top plate coupling together a first node of each of said capacitors; a coarse switch operable to selectively couple said top plate to said input of said coarse comparator circuit; and a fine switch operable to selectively couple said top plate to said input of said fine comparator circuit.

Claim 15

The method of claim 8, wherein said step of generating a predetermined number of the most significant of the bits comprises the steps of: sequentially comparing a voltage on said top plate of said capacitor array to a threshold voltage associated with the coarse comparator circuit; and logging the results of said step of sequentially comparing in a storage circuit, the results comprising the predetermined number of the most significant bits of the digital value.

Claim 16

The method of claim 8 wherein said step of generating the remaining bits comprises the steps of: sequentially comparing a voltage on said top plate of said capacitor array to a threshold voltage associated with the fine comparator circuit; and logging the results of said step of sequentially comparing in a storage circuit, the results comprising the remaining bits of the digital value.

Claim 19

The method of claim 11 and further comprising the steps of: redetermining a first value of the least significant bit determined using the coarse comparator using the fine comparator; storing the result of said step of redetermining; determining a second value of the least significant bit determined using the coarse comparator with the predetermined number of capacitors corresponding to the predetermined number of most significant bits in the digital value coupled such that a value of one greater than the value determined using the coarse comparator is represented; and selectively correcting the digital value logged in the storage circuit responsive to said steps of redetermining and determining, the first and second values indicative of the accurate value for the least significant bit determined by the coarse comparator.