Higher order interpolation for digital-to-analog conversion

Claim 2

An improved digital-to-analog converter comprising an input register for temporarily storing digital signals therein and for supplying said digital signals to a first accumulator for a first stream of most significant bits and the remaining bits as error bits, said first accumulator operating at a predetermined rate faster than said input register and means for converting the digital signals to analog form, the improvement comprising a second accumulator for receiving said error bits from said first accumulator as its input signal and for producing a second stream of most significant bits, a digital circuit for differentiating said second most significant bits, a binary adder for adding said most significant bits from said first accumulator and said second most significant bits from said second accumulator for producing a digital signal substantially free from truncation noise.

Claim 3

The converter of claim 1 wherein said digital circuit for differentiating said second most significant bits from said second accumulator comprises a register which operates at the same rate as said first accumulator and a subtracter.

Claim 4

The converter of claim 1 wherein said second accumulator comprises a second binary adder for receiving said error bits from said first accumulator, for generating said second most significant bits and for returning error bits comprising the bits other than said second most significant bits to a second feedback register which operates at the same rate as said first accumulator.

Claim 5

An improved digital-to-analog converter comprising an input register for temporarily storing digital signals therein and for supplying said digital signals to a first accumulator which has a first binary adder for receiving said digital signals from said first input register, for generating most significant bits, and for returning the remaining bits as first error bits to a first feedback register which operates at a rate faster than said input register and means for converting said digital signals to analog signals, said improvement comprising a first forward register which operates at the same rate as said first accumulator for temporarily storing said most significant bits and first means for converting said most significant bits from digital to analog form, a second accumulator for receiving said first error bits from said first binary adder of said first accumulator and for generating second most significant bits, a second forward register which operates at the same rate as said first accumulator for temporarily storing said second most significant bits and second means for converting said second most significant bits from digital to analog form, and means for amplifying said analog signals.

Claim 6

An improved digital-to-analog converter comprising an input register for temporarily storing digital signals therein and for supplying said digital signals to a first accumulator which has a first binary adder for receiving said digital signals from said first input register, for generating most significant bits, and for returning the remaining bits as first error bits to a first feedback register which operates at a rate faster than said input register and means for converting said digital signals to analog signals, said improvement comprising a first forward register which operates at the same rate as said first accumulator for temporarily storing said most significant bits and first means for converting said most significant bits from digital to analog form, a second accumulator for receiving said first error bits from said first binary adder of said first accumulator and for generating second most significant bits, a second forward register which operates at the same rate as said first accumulator for temporarily storing said second most significant bits and second means for converting said second most significant bits from digital to analog form, and means for amplifying said analog signals.

Claim 7

The converter of claim 4 wherein said first and second means for converting said most significant bits and said second most significant bits, respectively, together comprise a resistor capacitor (RC) filter, said most significant bits being supplied to one end of said resistor of said RC filter and said second most significant bits being supplied to one end of said capacitor or said RC filter and the other ends of said resistor and said capacitor being connected together with the input of said amplifier.

Claim 8

The converter of claim 5 wherein said amplifier has an input resistor sufficiently large to protect said amplifier against spurious signals.

Claim 9

The converter of claim 4 wherein said second accumulator comprises a second binary adder for receiving said first error bits from said first binary adder of said first accumulator, for generating said second most significant bits and for returning said second error bits to a second feedback register which operates at the same rate as said first accumulator.

Claim 10

An improved method for interpolating output values in a digital-to-analog converter comprising the steps of generating a first stream of most significant bits in a first accumulator from the digital bits which are input to said first accumulator the remaining bits being first error bits and being further processed in said first accumulator, wherein said improvement comprises the steps of generating a second stream of most significant bits in a second accumulator from said first error bits and processing the remaining bits further, digitally differentiating said most significant bits from said second accumulator, and digitally adding said differentiated most significant bits from said second accumulator with said most significant bits from said first accumulator, thereby substantially reducing the truncation noise caused by said converter.

Claim 11

An improved method for interpolating output values in a digital-to-analog converter comprising the steps of generating a first stream of most significant bits in a first accumulator from the digital bits which are input to said first accumulator the remaining bits being first error bits and being further processed in said first accumulator, wherein said improvement comprises the steps of generating a second stream of most significant bits in a second accumulator from said first error bits and processing the remaining bits further, digitally differentiating said most significant bits from said second accumulator, and digitally adding said differentiated most significant bits from said second accumulator with said most significant bits from said first accumulator, thereby substantially reducing the truncation noise caused by said converter.

Claim 12

An improved method for interpolating output values using two level conversion in a digital-to-analog converter comprising the steps of processing the digital bits in a first accumulator to generate most significant bits representing the signal contaminated with truncation noise, the remaining error bits being further processed, wherein the improvement comprises the steps of processing said error bits in a second accumulator to generate most significant bits which are used to compensate for the truncation noise in said most significant bits from said first accumulator, differentiating said most significant bits from said second accumulator after converting said most significant bits from said second accumulator from digital to analog form, converting said most significant bits from said first accumulator to analog form, combining said most significant bits from said first accumulator and said differentiated most significant bits from said second accumulator and amplifying the resulting signal which is then filtered to obtain the desired analog signal which is free from substantially all truncation noise.

Claim 13

An improved method for interpolating output values using two level conversion in a digital-to-analog converter comprising the steps of processing the digital bits in a first accumulator to generate most significant bits representing the signal contaminated with truncation noise, the remaining error bits being further processed, wherein the improvement comprises the steps of processing said error bits in a second accumulator to generate most significant bits which are used to compensate for the truncation noise in said most significant bits from said first accumulator, differentiating said most significant bits from said second accumulator after converting said most significant bits from said second accumulator from digital to analog form, converting said most significant bits from said first accumulator to analog form, combining said most significant bits from said first accumulator and said differentiated most significant bits from said second accumulator and amplifying the resulting signal which is then filtered to obtain the desired analog signal which is free from substantially all truncation noise.

Claim 14

A compound interpolator comprising a first interpolator for receiving a digital signal and for producing a first digital output and an error signal, a second interpolator for receiving said error signal and for producing a second digital output, a differentiating circuit for producing the derivative of said second digital output, a combining circuit for summing said first digital output with said derivative of said second digital output to produce the output signal from said compound interpolator.

Claim 15

A compound interpolator comprising a first interpolator for receiving a digital signal and for producing a first digital output and an error signal, a second interpolator for receiving said error signal and for producing a second digital output, a differentiating circuit for producing the derivative of said second digital output, a combining circuit for summing said first digital output with said derivative of said second digital output to produce the output signal from said compound interpolator.

Claim 16

The compound interpolator of claim 10 wherein said first interpolator is an accumulator for producing said first digital output which comprises a stream of most significant bits and for producing said error signal which comprises a stream of least significant bits.

Claim 17

The compound interpolator of claim 11 wherein said second interpolator is an accumulator for producing said second digital output which comprises a second stream of most significant bits.

Claim 18

The compound interpolator of claim 11 wherein said second second interpolator comprises two accumulators for producing said second digital output which comprises a second stream of most significant bits.

Claim 19

A digital-to-analog converter comprising an input register for temporarily storing digital signals therein and for supplying said digital signals to a compound interpolator, said compound interpolator operating at a predetermined rate faster than input register, and means for converting the output signal from said interpolator to analog form, compound interpolator comprising a first interpolator for receiving said digital signals and for producing a first digital output and an error signal, a second interpolator for receiving said error signal and for producing a second digital output, a differentiating circuit for producing the derivative of said second digital output, a combining circuit for summing said first digital output with said derivative of said second digital output to produce said output signal from said compound interpolator.

Claim 20

A digital-to-analog converter comprising an input register for temporarily storing digital signals therein and for supplying said digital signals to a compound interpolator, said compound interpolator operating at a predetermined rate faster than input register, and means for converting the output signal from said interpolator to analog form, compound interpolator comprising a first interpolator for receiving said digital signals and for producing a first digital output and an error signal, a second interpolator for receiving said error signal and for producing a second digital output, a differentiating circuit for producing the derivative of said second digital output, a combining circuit for summing said first digital output with said derivative of said second digital output to produce said output signal from said compound interpolator.