Patent US5005067A successfully refreshed from Google Patents.
US5005067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Fujifilm Business Innovation Corp
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Filing: 1988-03-07
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Granted: 1991-04-02
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Expires: 2008-03-07
Abstract
Abstract A semiconductor integrated circuit providing a novel patterned multilayered wiring structure to enhance the degree of the integration of the circuit and the speed of the operation. The structure includes at least one first interlaid electric insulator film on the wall of the contact portion of a first wiring layer and its vicinity, a second interlaid electric insulator film, which reacts distinctly to the etching process utilized from the first interlaid electric insulator film, is provided on a substrate.
Inventors
- 👤 Yasushi Sakata
- 👤 Toshimichi Iwamori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
321 words
A semiconductor integrated circuit comprising: a substrate; a first electrically conductive wiring layer formed on a surface of the substrate, said first wiring layer being substantially rectangular in cross section with an upper surface having a laterally extending dimension defining the width dimension and opposite sidewalls defining the height dimension; a first interlaid electrically insulating layer having a first etching speed overlaying at least a portion of the substrate on opposite sides of the first wiring layer, and being contiguous to both sidewalls of the first wiring layer, said first insulating layer longitudinally extending outwardly from the sidewalls of the first wiring layer in a direction substantially parallel with the width dimension of the first electrically conductive wiring layer defining a maximum width dimension contiguous to the substrate and having a maximum thickness dimension corresponding to the defined height dimension of said first wiring layer, said thickness dimension varying as a function of said width dimension; a second interlaid electrically insulating layer having a second etching speed different than the first etching speed overlaying at least a portion of the first insulating layer on each side of the opposite sidewalls of the first wiring layer, said second insulating layer having opposing edges spaced from each other, said spaced opposing edges defining boundaries for an opening for exposing at least a portion of the upper surface of the first wiring layer through said opening; and a second electrically conductive wiring layer overlaying said second insulating layer and filling said opening of the second insulating layer for making electrical contact with the first wiring layer, at least a portion of the first insulating layer protecting the substrate from electrical contact with the second wiring layer at times when at least one of the spaced opposing edges of the second insulating layer is spaced from the upper surface of the first wiring layer, wherein said first interlaid insulating layer includes a silicon nitride film.
Claim 2
Dependent Claim
321 words
A semiconductor integrated circuit comprising: a substrate; a first electrically conductive wiring layer formed on a surface of the substrate, said first wiring layer being substantially rectangular in cross section with an upper surface having a laterally extending dimension defining the width dimension and opposite sidewalls defining the height dimension; a first interlaid electrically insulating layer having a first etching speed overlaying at least a portion of the substrate on opposite sides of the first wiring layer, and being contiguous to both sidewalls of the first wiring layer, said first insulating layer longitudinally extending outwardly from the sidewalls of the first wiring layer in a direction substantially parallel with the width dimension of the first electrically conductive wiring layer defining a maximum width dimension contiguous to the substrate and having a maximum thickness dimension corresponding to the defined height dimension of said first wiring layer, said thickness dimension varying as a function of said width dimension; a second interlaid electrically insulating layer having a second etching speed different than the first etching speed overlaying at least a portion of the first insulating layer on each side of the opposite sidewalls of the first wiring layer, said second insulating layer having opposing edges spaced from each other, said spaced opposing edges defining boundaries for an opening for exposing at least a portion of the upper surface of the first wiring layer through said opening; and a second electrically conductive wiring layer overlaying said second insulating layer and filling said opening of the second insulating layer for making electrical contact with the first wiring layer, at least a portion of the first insulating layer protecting the substrate from electrical contact with the second wiring layer at times when at least one of the spaced opposing edges of the second insulating layer is spaced from the upper surface of the first wiring layer, wherein said first interlaid insulating layer includes a silicon nitride film.
Claim 3
Dependent Claim
20 words
A semiconductor intergrated circuit according to the claim 1, wherein said first interlaid insulating layer is made of silicon nitride.
Claim 4
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 1, wherein said second wiring layer is made of aluminum.
Claim 5
Dependent Claim
312 words
A semiconductor integrated circuit comprising: a substrate; a first electrically conductive wiring layer formed on a surface of the substrate, said first wiring layer being substantially rectangular in cross section with an upper surface having a laterally extending dimension defining the width dimension and opposite sidewalls defining the height dimension; a first interlaid electrically insulating layer having an first etching speed overlaying at least a portion of the substrate on opposite sides of the first wiring layer, and being contiguous to both sidewalls of the first wiring layer, said first insulating layer longitudinally extending outwardly from the sidewalls of the first wiring layer in a direction substantially parallel with the width dimension of the first electrically conductive wiring layer defining a maximum width dimension contiguous to the substrate and having a maximum thickness dimension corresponding to the defined height dimension of said first wiring layer, said thickness dimension varying as a function of said width dimension; a second interlaid electrically insulating layer having a second etching speed different than the first etching speed overlaying at least a portion of the first insulating layer on each side of the opposite sidewalls of the first wiring layer, said second insulating layer having opposing edges spaced from each other a distance, said spaced opposing edges defining boundaries for an opening for exposing at least a portion of the upper surface of the first wiring layer through said opening; and a second electrically conductive wiring layer overlaying said second insulating layer and filling said opening of the second insulating layer for making electrical contact with the first wiring layer, at least a portion of the first insulating layer protecting the substrate, from electrical contact with the second wiring layer at times when at least one of the spaced opposing edges of the second insulating layer is spaced from the upper surface of the first wiring layer.
Claim 6
Dependent Claim
312 words
A semiconductor integrated circuit comprising: a substrate; a first electrically conductive wiring layer formed on a surface of the substrate, said first wiring layer being substantially rectangular in cross section with an upper surface having a laterally extending dimension defining the width dimension and opposite sidewalls defining the height dimension; a first interlaid electrically insulating layer having an first etching speed overlaying at least a portion of the substrate on opposite sides of the first wiring layer, and being contiguous to both sidewalls of the first wiring layer, said first insulating layer longitudinally extending outwardly from the sidewalls of the first wiring layer in a direction substantially parallel with the width dimension of the first electrically conductive wiring layer defining a maximum width dimension contiguous to the substrate and having a maximum thickness dimension corresponding to the defined height dimension of said first wiring layer, said thickness dimension varying as a function of said width dimension; a second interlaid electrically insulating layer having a second etching speed different than the first etching speed overlaying at least a portion of the first insulating layer on each side of the opposite sidewalls of the first wiring layer, said second insulating layer having opposing edges spaced from each other a distance, said spaced opposing edges defining boundaries for an opening for exposing at least a portion of the upper surface of the first wiring layer through said opening; and a second electrically conductive wiring layer overlaying said second insulating layer and filling said opening of the second insulating layer for making electrical contact with the first wiring layer, at least a portion of the first insulating layer protecting the substrate, from electrical contact with the second wiring layer at times when at least one of the spaced opposing edges of the second insulating layer is spaced from the upper surface of the first wiring layer.
Claim 7
Dependent Claim
48 words
A semiconductor integrated circuit according to claim 1, wherein said first interlaid insulating layer further includes a spin-on-glass film overlaying said silicon nitride film and wherein said thickness dimension of the first interlaid insulating layer decreases as a function of said width dimension of the first insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-04-01 | 1994-10-01 | 1995-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-04-01 | 1998-10-01 | 1999-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-04-01 | 2002-10-01 | 2003-04-02 | $7700.00 | Window Closed / Lapsed |