Apparatus for receiving digital signal

Claim 2

Apparatus for receiving a modulated input digital signal having synchronization data inserted at predetermined intervals and including a timing signal in synchronism with the synchronization data and developed from the modulated input digital signal, said apparatus comprising: means responsive to said synchronization data for generating detection signals that indicate a sampling frequency of said modulated input digital signal and for generating a first error signal upon failure to detect said sampling frequency; first signal generating means for generating signals having selected frequencies and selecting one of the generated signals as a first reference signal in response to said detection signals; a phase-locked loop; second signal generating means responsive to an output signal of said phase-locked loop for generating, as an output, a second reference signal in synchronism with said synchronization data; means responsive to said modulated input digital signal for producing a demodulated signal and for producing a second error signal in case of a demodulation error; and switching means responsive to said first and second error signals for supplying said first reference signal to said phase-locked loop in case of failure to detect said sampling frequency or in case of a demodulation error and otherwise normally supplying said second reference signal to said phase-locked loop.

Claim 3

Apparatus according to claim 1, wherein said modulated input digital signal contains two audio samples within one sampling period.

Claim 4

Apparatus according to claim 1, wherein said modulated input digital signal undergoes a series of inversions during a plurality of inversion intervals and said means for generating detection signals includes means for detecting a maximum-inversion interval in said modulated input digital signal and producing a maximum-inversion interval output signal fed to said first signal generating means.

Claim 5

Apparatus according to claim 1, wherein said first signal generating means includes a stable clock signal generator producing said signals having selected frequencies.

Claim 6

Apparatus according to claim 4, further comprising a clock control circuit and an unlocked state detector receiving a detection signal from said means for generating detection signals, whereby said clock generator is turned off by said clock control circuit in response to a signal from said unlocked state detector when said phase-locked loop is in a locked condition.

Claim 7

Apparatus for receiving a modulated input digital signal having synchronization data at predetermined intervals and a timing signal in synchronism with the synchronization data, said apparatus comprising: detection means responsive to said synchronization data for generating a plurality of detection signals that indicate a sampling frequency of said modulated input digital signal and for generating a first error signal upon failure to detect said sampling frequency; first signal generating means for generating signals having selected frequencies and producing as an output one of the generated signals as a first reference signal in response to said detection signals indicative of the sampling frequency of the input signal; a phase-locked loop; second signal generating means responsive to an output signal of said phase-locked loop for generating, as an output, a second reference signal in synchronism with said synchronization data; means responsive to said modulated input digital signal for producing a demodulated signal and for producing a second error signal in case of a demodulation error; and selector means responsive to said first and second error signals for selectively supplying said first reference signal to said phase-locked loop in case of a failure to detect sad sampling frequency or in case of a demodulation error and otherwise normally supplying said second reference signal to said phase-locked loop.

Claim 8

Apparatus for receiving a modulated input digital signal having synchronization data at predetermined intervals and a timing signal in synchronism with the synchronization data, said apparatus comprising: detection means responsive to said synchronization data for generating a plurality of detection signals that indicate a sampling frequency of said modulated input digital signal and for generating a first error signal upon failure to detect said sampling frequency; first signal generating means for generating signals having selected frequencies and producing as an output one of the generated signals as a first reference signal in response to said detection signals indicative of the sampling frequency of the input signal; a phase-locked loop; second signal generating means responsive to an output signal of said phase-locked loop for generating, as an output, a second reference signal in synchronism with said synchronization data; means responsive to said modulated input digital signal for producing a demodulated signal and for producing a second error signal in case of a demodulation error; and selector means responsive to said first and second error signals for selectively supplying said first reference signal to said phase-locked loop in case of a failure to detect sad sampling frequency or in case of a demodulation error and otherwise normally supplying said second reference signal to said phase-locked loop.

Claim 9

Apparatus according to claim 6, wherein said modulated input digital signal undergoes a series of inversions during plurality of inversion intervals and said means for generating detection signals generates as one of said plurality of detection signals a signal indicating a maximum-inversion interval in said input digital signal.

Claim 10

Apparatus according to claim 7, wherein said first signal generating means includes a clock signal generator producing said signals having selected frequencies.

Claim 11

Apparatus according to claim 8, further comprising a clock signal generator control circuit and a state detector, said state detector receiving a detection signal indicating the locked state of said phase-locked loop from said detection means, whereby said clock signal generator is stopped by said clock signal generator control circuit in response to a signal from state detector when said phase-locked loop is in a locked condition.