Communication network and protocol for real-time control of mailing machine operations

Claim 2

In a communication network having a first, second, third, and fourth node comprising: said nodes each having a transmit pin, a receive pin and programmable microprocessor means programmed for generating a message at said transmit pin and for receiving messages presented at said receive pin; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second and third nodes and said receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and enabled thereby to respond only to said uniquely addressed message.

Claim 3

A communication network as claimed in claim 1 said programmable microprocessor means is further programmed for providing message error detection means for detecting whether a message transmitted from a transmitting one of said nodes is identical to said message received by said receiving one of said nodes.

Claim 4

A communication network as claimed in claim 2 said programmable microprocessor means is further programmed for providing message repeat means for causing said transmitting one of said nodes to retransmit said message should said error detection means detect a message error.

Claim 5

A communication network as claimed in claims 1, 2 or 3, said programmable microprocessor means is further programmed for providing contention means for determining whether the communication line is clear for nodal communication.

Claim 6

In a communication network having a first, second, third, and fourth node comprising: each of said nodes having a transmit pin, a receive pin and programmable microprocessor means for generating message at said transmit pin and for receiving messages presented at said receive pin; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second and third nodes and said receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and enabled thereby to respond only to said uniquely addressed message such that a first one of said nodes transmits an addressed message to a specific one of said other nodes, said other node receiving said addressed message and thereafter transmitting a response to said first one of said nodes thereafter said first one of said nodes transmitting an information message to said addressed node.

Claim 7

In a communication network having a first, second, third, and fourth node comprising: each of said nodes having a transmit pin, a receive pin and programmable microprocessor means for generating message at said transmit pin and for receiving messages presented at said receive pin; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second and third nodes and said receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and enabled thereby to respond only to said uniquely addressed message such that a first one of said nodes transmits an addressed message to a specific one of said other nodes, said other node receiving said addressed message and thereafter transmitting a response to said first one of said nodes thereafter said first one of said nodes transmitting an information message to said addressed node.

Claim 8

A communication network as claimed in claim 5 said programmable microprocessor means is further programmed for providing error detection means for detecting whether a message transmitted from a transmitting one of said nodes is identical to said message received by said receiving one of said nodes.

Claim 9

A communication network as claimed in claim 6 said programmable microprocessor means is further programmed for providing message repeat means for causing said transmitting one of said nodes to retransmit said message should said error detection means detect a message error.

Claim 10

In a communication network having a first, second, third, and fourth nodes comprising: each of said nodes having a transmit pin, a receive pin and programmable microprocessor means for generating message at said transmit pin and for receiving messages presented at said receive pin; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second node and third node and receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and to respond only to said uniquely addressed messages such that a first one of said nodes transmits an addressed message to a specific one of said other nodes, said other node receiving said addressed message and thereafter transmitting a response to said first one of said nodes thereafter said first one of said nodes addressed node; said microprocess of said respective nodes being programmed to provide connection means for determining whether the communication line is clear for nodal communication.

Claim 11

In a communication network having a first, second, third, and fourth nodes comprising: each of said nodes having a transmit pin, a receive pin and programmable microprocessor means for generating message at said transmit pin and for receiving messages presented at said receive pin; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second node and third node and receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and to respond only to said uniquely addressed messages such that a first one of said nodes transmits an addressed message to a specific one of said other nodes, said other node receiving said addressed message and thereafter transmitting a response to said first one of said nodes thereafter said first one of said nodes addressed node; said microprocess of said respective nodes being programmed to provide connection means for determining whether the communication line is clear for nodal communication.

Claim 12

In a communication network as claimed in claim 8 said programmable microprocessor means is further programmed for providing error detection means for detecting whether a message transmitted from a transmitting one of said nodes is identical to said message received by said receiving node.

Claim 13

In a communication network as claimed in claim 9 wherein said error detection means comprises said microprocessor of said transmitting node being programmed to compute a message cyclic redundancy binary and transmit said binary to said receiving node, said microprocessor of said receiving node being programmed to compute said receive message cyclic redundancy binary and comparing said computed binary with said transmitted binary.

Claim 14

In a communication network as claimed in claim 10 said programmable microprocessor means is further programmed for providing message repeat means for causing said transmitting mode to retransmit said message should said comparison of said cyclic redundancy binaries not match.

Claim 15

In a communication network as claimed in claim 10 wherein said contention means comprises said microprocessor being programmed to transmit a message byte such that a particular bit location is set only when the address message is transmitted, and to receive and respond to only those messages having the proper address followed by a message stream not having the particular bit location set.

Claim 16

In a communication network having a first, second, third, and fourth node comprising: each of said nodes having a transmit pin, a receive pin and programmable microprocessor means for generating messages at said transmit pin and for receiving messages presented at said receive pin; said first and second nodes being programmed to independently generate messages; said third node being able to generate a message only in response to a message from said first node; said fourth node being programmed to independently generate message only to said second node; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second node and third node and said receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and to respond only to said uniquely addressed messages such that a first one of said nodes transmits an addressed message to a specific one of said other nodes, said other node receiving said addressed message and thereafter transmitting a response to said first one of said nodes thereafter said first one of said nodes transmitting an information message to said addressed node; said microprocessor of said respective nodes being programmed to provide contention means for determining whether the communication line is clear for nodal communication.

Claim 17

In a communication network having a first, second, third, and fourth node comprising: each of said nodes having a transmit pin, a receive pin and programmable microprocessor means for generating messages at said transmit pin and for receiving messages presented at said receive pin; said first and second nodes being programmed to independently generate messages; said third node being able to generate a message only in response to a message from said first node; said fourth node being programmed to independently generate message only to said second node; said transmit pin of said first node being in line communication with said receive pin of said second node and third node and the transmit pin of said fourth node, and said receive pin of said first node being in line communication with said transmit pin of said second node and third node and said receive pin of said fourth node; said microprocessor of said respective nodes being programmed to receive a message at said receiving pin uniquely addressed to the said respective node and to respond only to said uniquely addressed messages such that a first one of said nodes transmits an addressed message to a specific one of said other nodes, said other node receiving said addressed message and thereafter transmitting a response to said first one of said nodes thereafter said first one of said nodes transmitting an information message to said addressed node; said microprocessor of said respective nodes being programmed to provide contention means for determining whether the communication line is clear for nodal communication.

Claim 18

A communication network as claimed in claim 13 said programmable microprocessor means is further programmed for providing error detection means for detecting whether said message transmitted from a transmitting one of said nodes is identical to said message received by said receiving one of said nodes.

Claim 19

In a communication network as claimed in claim 14 wherein said error detection means comprises said microprocessor of said transmitting node being programmed to compute a message cyclic redundancy binary and transmit said binary to said receiving node, said microprocessor of said receiving node being programmed to computer said receive message cyclic redundancy binary and comparing said computed binary with said transmitted binary.

Claim 20

In a communication network as claimed in claim 15 said programmable microprocessor means is further programmed for providing message repeat means for causing said node generating said message to retransmit said message should said comparison of said cyclic redundancy binaries not match.

Claim 21

In a communication network as claimed in claim 13 wherein said contention means comprises said microprocessor being programmed to transmit a message byte such that a particular bit location is set only when the address message is transmitted, and to receive and respond to only those messages having the proper address followed by a message stream not having the particular bit location set.