US4750176A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single-channel communication bus system and station for use in such system
Assignee: US Philips Corp
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Filing: 1986-06-30
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Granted: 1988-06-07
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Expires: 2006-06-30
Abstract
Abstract The invention relates to a single-channel digital communication bus system and to a station for use in such system. Only a single physical interconnection between the stations is present for transferring the data. Bit synchronization is effected either in that the data is self-clocking or by a second, clock lead. The data channel realizes an AND-function. The transmission of a message by a master station is answered by an addressed slave by an acknowledge signal train. The acknowledge signal train has a plurality of bits, inclusive of error protection bits. Error protection may be effected by transmitting a series of mutually identical bits, or by means of a CRC signal subtrain. The acknowledge may be positive, negative or a "no acknowledge" signal train.
Inventors
- 👤 Evert D. Van Veldhuizen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:32
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/12; H04L1/16; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0635; H04J3/0638; H04L2001/0092; H04L2001/0094; H04L2001/125
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
130 words
A single-channel digital communication bus system having a master station and at lease one slave station interconnected for communication by said bus, said bus constituting a logic-AND-function said master station having first transmitting means for transmitting a message on said bus comprising at least an address signal train followed by a data signal train and an error protection signal train, said slave station comprising second transmitting means for receiving such address cum data cum error protection signals train as slave station and transmitting on said bus a multiple acknowledge signal train inclusive of second error protection signals allowing for correction of at least one bit, and wherein all of said signal trains are synchronized by means of at least one signal transition at a predetermined point within each bit cell.
Claim 2
Dependent Claim
130 words
A single-channel digital communication bus system having a master station and at lease one slave station interconnected for communication by said bus, said bus constituting a logic-AND-function said master station having first transmitting means for transmitting a message on said bus comprising at least an address signal train followed by a data signal train and an error protection signal train, said slave station comprising second transmitting means for receiving such address cum data cum error protection signals train as slave station and transmitting on said bus a multiple acknowledge signal train inclusive of second error protection signals allowing for correction of at least one bit, and wherein all of said signal trains are synchronized by means of at least one signal transition at a predetermined point within each bit cell.
Claim 3
Dependent Claim
51 words
A single-channel digital communication bus system as claimed in claim 1, wherein said acknowledge cum second error protection signal train constitutes a single signal train having a first plurality of bit positions for representing a positive acknowledge signal and, a second plurality of bit positions for representing a negative acknowledge signal.
Claim 4
Dependent Claim
33 words
A single-channel digital communication bus system as claimed in claim 2, wherein said first and second plurality of bit positions are mutually exclusive and said second plurality is larger than said first plurality.
Claim 5
Dependent Claim
58 words
A slave station for use in a single-channel digital communication system as claimed in claim 3, comprising transmitting means for transmitting an acknowledge byte having a first number of bit positions for by means of zeroes therein signalling a positive acknowledge and a second number of bit positions for by means of zeroes therein signalling a negative acknowledge.
Claim 6
Dependent Claim
30 words
A slave station as claimed in claim 4, wherein said transmitting means have a state for signalling a "no acknowledge" signal by means of exclusively transmitting "ones" within said train.
Claim 7
Dependent Claim
38 words
A slave station as claimed in claim 5, having counting means for upon being addressed counting the number of times of consecutively transmitting a negative acknowledge and upon reaching a predetermined count thereafter transmitting a "no acknowledge" signal.
Claim 8
Dependent Claim
58 words
A slave station for use in a single-channel digital communication system as claimed in claim 2, comprising transmitting means for transmitting an acknowledge byte having a first number of bit positions for by means of zeroes therein signalling a positive acknowledge and a second number of bit positions for by means of zeroes therein signalling a negative acknowledge.
Claim 9
Dependent Claim
30 words
A slave station as claimed in claim 7, wherein said transmitting means have a state for signalling a "no acknowledge" signal by means of exclusively transmitting "ones" within said train.
Claim 10
Dependent Claim
38 words
A slave station as claimed in claim 8, having counting means for upon being addressed counting the number of times of consecutively transmitting a negative acknowledge and upon reaching a predetermined count thereafter transmitting a "no acknowledge" signal.
Claim 11
Dependent Claim
60 words
A master station for use with a slave station as claimed in claim 7, 8, 9, 4, 5 or 6, having receiving means for upon reception of a predetermined minimum number of zeroes within said second number of bit poisitions recognizing a negative acknowledge signal in spite of an arbitrary content of any remaining bit position within said acknowledge byte.
Claim 12
Dependent Claim
93 words
A single-channel digital communication system as claimed in claim 1, wherein said acknowledge cum second error protection signal train comprises a sequence of signal subtrains, a first subtrain of exclusively "one" bits in combination with a second subtrain of not-all-ones constituting a slave station data signalling a positive acknowledge, a second subtrain of exclusively "one" bits in combination with a first subtrain of not-all-ones constituting a slave station data signalling a negative acknowledge; both a negative acknowledge and a positive acknowledge being completed by a third subtrain comprising an error detection bit sequence.
Claim 13
Dependent Claim
21 words
A single-channel digital communication system as claimed in claim 11, wherein said slave station data represent a particular slave station address.
Claim 14
Dependent Claim
34 words
A single-channel digital communication bus system as claimed in claim 11 or 12, wherein error detection bit sequence is a CRC bit sequence as calculated over either a negative or a positive acknowledgement signal.
Claim 15
Dependent Claim
69 words
A slave station for use in a single-channel digital communication bus system as claimed in claim 11, furthermore comprising conflict detecting means for during said first and second subtrains detecting a zero bus bit as representing a discrepancy with respect to its own transmitted bit in the bit position in question, said conflict detecting means thereupon causing termination of transmitting the acknowledge signal train by the station in question.
Claim 16
Dependent Claim
39 words
A slave station for use in a single-channel digital communication bus system as claimed in claim 11, wherein said transmitting means has a state for transmitting a "no acknowledge" signal by means of exclusively transmitting "ones" within said train.
Claim 17
Dependent Claim
27 words
A master station for use with a slave station as claimed in claim 15 having means for upon receiving non-conforming error protection subtrain repeating its own message.
Claim 18
Dependent Claim
36 words
A master station as claimed in claim 16, furthermore having a detector for upon reception of two subtrains comprising only "one" bits detecting a "no acknowledge" signal on the basis of a non-conforming error detection subtrain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-07 | 1991-12-07 | 1992-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-07 | 1995-12-07 | 1996-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-07 | 1999-12-07 | 2000-06-07 | $7700.00 | Window Closed / Lapsed |