Television receiver including a tuning circuit which comprises a frequency synthesis circuit

Claim 1

A television receiver including a tuning circuit which comprises a frequency synthesis circuit in which the tuning of a tuning oscillator is obtained by means of a frequency divider which is adjustable by means of a tuning datum, said tuning datum being corrigible by means of a frequency detection circuit when receiving a television signal identified as being correct by an identification circuit, said frequency detection circuit being coupled to an output of an intermediate frequency amplifier, an input of which is coupled to an output of the tuning circuit, characterized in that the frequency detection circuit is a counter which is coupled at least via a measuring gate to an output of a reference signal oscillator which forms part of a phase-coupled loop coupled to an output of the intermediate frequency amplifier, an output of said reference signal oscillator being further coupled to a reference signal input of a synchronous video signal detector while the measuring gate is operable by means of a measuring gate signal synchronized with the line frequency of a received television signal.