← Back to Patent Explorer
US5003357A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor light emitting device

Assignee: Samsung Semiconductor and Telecomunications Co Ltd
•
Filing: 1990-01-17
•
Granted: 1991-03-26
•
Expires: 2010-01-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract This invention is related to a semiconductor light emitting device integrated with a Si-heat sink which contains not only a beam deflector but also the driving integrated circuits. A semiconductor light emitting device comprising a Si-substrate 2, V-groove 3 etched into substrate 2 and a beam deflector 9 on the wall of V-groove 3 wherein the transistor 22 for the driving and control on said Si-substrate is integrated so that light emitting device 1 and said integrated circuit are integrally mounted. The advantage of this invention is that the integration of the driving transistor with the light emitting device in the same package head reduces the packaging and bonding problems. Obtained is a compact optical system which easily radiates the heat dissipated by devices. This is in contrast to conventional light emitting devices which use the Si-substrate only as a mount and beam deflector.

Inventors

  • 👤 Bun-Joong Kim
  • 👤 Jun-Young Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 08:33
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/80; H10H20/85; H10H20/855; H10W; H10W90/00; H10H20/81; H10H20/817; H10H20/8506; H10H20/857; H10H20/856; H10H20/858; H10H20/8581; H10H20/8583; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/551; H10W72/552; H10W72/5522

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 128 words
An integrated semiconductor light emitting device comprising: a silicon substrate having a major surface; an integrated circuit comprising at least one transistor formed in said major surface of the silicon substrate; a V-shaped groove etched in the major surface of the silicon substrate adjacent to said integrated circuit; a passivation layer formed simultaneously in said V-shaped groove and over said transistor; a reflective metallic layer formed above said passivation layer in said V-shaped groove; a semiconductor light emitting means mounted in said V-shaped groove, said V-shaped groove reflecting light emanating from said light emitting means; and an electrical interconnection between said semiconductor light emitting means and said integrated circuit connecting said circuit and light emitting means together, whereby said integrated circuit drives and controls said light emitting means.
Claim 2
Dependent Claim 128 words
An integrated semiconductor light emitting device comprising: a silicon substrate having a major surface; an integrated circuit comprising at least one transistor formed in said major surface of the silicon substrate; a V-shaped groove etched in the major surface of the silicon substrate adjacent to said integrated circuit; a passivation layer formed simultaneously in said V-shaped groove and over said transistor; a reflective metallic layer formed above said passivation layer in said V-shaped groove; a semiconductor light emitting means mounted in said V-shaped groove, said V-shaped groove reflecting light emanating from said light emitting means; and an electrical interconnection between said semiconductor light emitting means and said integrated circuit connecting said circuit and light emitting means together, whereby said integrated circuit drives and controls said light emitting means.
Claim 3
Dependent Claim 38 words
The integrated semiconductor light emitting device of claim 1 wherein said electrical interconnection includes an intermetallic diffusion layer between said reflective metallic layer and said integrated circuit, said intermetallic diffusion layer formed before forming said reflective metallic layer.

References Cited (Backward Citations)

US3883772A Cited
US4013915A Cited
US4310362A Cited
US4486945A Cited
JPS59108382A Cited
JPS60137076A Cited
DE3404875A1 Cited
US4691214A Cited
JPS6074487A Cited
JPS6223163A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-03-25 1994-09-24 1995-03-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-03-25 1998-09-24 1999-03-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-03-25 2002-09-24 2003-03-26 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag