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US5001669A
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Semiconductor memory circuit having dummy cells connected to twisted bit lines
Assignee: Oki Electric Industry Co Ltd
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Filing: 1989-07-26
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Granted: 1991-03-19
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Expires: 2009-07-26
Abstract
Abstract A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be sorted. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dummy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.
Inventors
- 👤 Shizuo Cho
- 👤 Masaru Uesugi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4099; G11C7/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
263 words
A semiconductor memory circuit comprising: a plurality of bit line pairs each having intersecting portions where bit lines in said pair cross each other; a plurality of pairs of memory word lines crossing the plurality of bit lines in a direction substantially perpendicular to said plurality of bit lines; a plurality of memory cells for storing charge corresponding to data to be stored in the memory, each of said memory cells being connected to a corresponding one of said memory word lines and a corresponding one of said bit lines at either (a) an intersection of one memory word line of said plurality of pairs of memory word lines with one bit line of said plurality of pairs of bit lines, or (b) an intersection of the other memory word line of said plurality of pairs of memory word lines with the other bit line of said plurality of pairs of bit lines; a pair of dummy word lines interposed between the intersecting portions of the bit lines and intersecting the plurality of pairs of bit lines in a direction substantially perpendicular to said plurality of pairs of bit lines; and a plurality of dummy cells individually connected between the pair of dummy word lines and the plurality of pairs of bit lines at intersections of one of said pair of dummy word lines and one bit line of said plurality of pairs of bit lines and at intersections of the other dummy word line of said pair of dummy word lines and the other bit line of said plurality of bit lines.
Claim 2
Dependent Claim
263 words
A semiconductor memory circuit comprising: a plurality of bit line pairs each having intersecting portions where bit lines in said pair cross each other; a plurality of pairs of memory word lines crossing the plurality of bit lines in a direction substantially perpendicular to said plurality of bit lines; a plurality of memory cells for storing charge corresponding to data to be stored in the memory, each of said memory cells being connected to a corresponding one of said memory word lines and a corresponding one of said bit lines at either (a) an intersection of one memory word line of said plurality of pairs of memory word lines with one bit line of said plurality of pairs of bit lines, or (b) an intersection of the other memory word line of said plurality of pairs of memory word lines with the other bit line of said plurality of pairs of bit lines; a pair of dummy word lines interposed between the intersecting portions of the bit lines and intersecting the plurality of pairs of bit lines in a direction substantially perpendicular to said plurality of pairs of bit lines; and a plurality of dummy cells individually connected between the pair of dummy word lines and the plurality of pairs of bit lines at intersections of one of said pair of dummy word lines and one bit line of said plurality of pairs of bit lines and at intersections of the other dummy word line of said pair of dummy word lines and the other bit line of said plurality of bit lines.
Claim 3
Dependent Claim
47 words
A memory circuit in accordance with claim 1, wherein the bit lines of any of the plurality of pairs of bit lines have the intersecting portions located in positions which correspond to positions between the intersecting portions of the pairs of bit lines which adjoin said pair.
Claim 4
Dependent Claim
55 words
A memory circuit in accordance with claim 2, wherein in any of the plurality of pairs of bit lines which has the memory cells between one of opposite ends and the intersecting portion closest to said end, the dummy cells and the dummy word lines are interposed between said end and said closest intersecting portion.
Claim 5
Dependent Claim
50 words
A memory circuit in accordance with claim 2, wherein the plurality of dummy cells are individually aligned with the intersecting portions of the bit line pairs which are adjacent to the bit line pairs associated with said plurality of dummy cells, in a direction parallel to the dummy word lines.
Claim 6
Dependent Claim
78 words
A memory circuit in accordance with claim 2, wherein said memory circuit is fabricated in a MOS configuration on a semiconductor substrate; the plurality of memory word lines and the pair of dummy word lines including polysilicon; the plurality of pairs of bit lines including metal except for the intersecting portions, one bit line of said plurality of bit lines including metal in the intersecting portions, the other bit line including a diffusion layer in the intersecting potions.
Claim 7
Dependent Claim
93 words
A memory circuit in accordance with claim 5, wherein each of the memory cells comprises a first MOS transistor and a first capacitor, said first MOS transistor comprising a source-drain path connected in series with said first capacitor and a control electrode connected to any of the memory word lines; each of the plurality of dummy cells comprising a second MOS transistor and a second capacitor, said second MOS transistor comprising a source-drain path connected in series with said second capacitor and a control electrode connected to any of the dummy word lines.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-18 | 1994-09-17 | 1995-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-18 | 1998-09-17 | 1999-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-18 | 2002-09-17 | 2003-03-19 | $7700.00 | Window Closed / Lapsed |