US4999770A — Command controlled multi-storage space protection…

Claim 1

Independent Claim 217 words

A data processing system for multi-address space control wherein when a main storage is to be accessed from a processor, a main storage protection is conducted by comparing by a comparator an access key output by said processor with a main storage key provided in the main storage, comprising: a first key register for storing a program status word key output by said processor; a second key register for storing an access key output by said processor in accordance with a data transfer instruction; a selector for selecting one of said first and second key register under control of said processor independently from storage access type; judging means coupled to said selector for judging whether a key selected by said selector is a predetermined value, allowing said processor to access said main storage irrespective of a value of said main storage key when the value of said selected key matches said predetermined value, and for comparing the value of said selected key to said main storage key; and pretesting means including a microprogram for executing a predetermined pretesting procedure, for setting said predetermined value in said second key register as a key for pretesting a data transfer between a plurality of address spaces when a key included in a transfer instruction coincides with said main storage key.

Claim 2

Dependent Claim 217 words

A data processing system for multi-address space control wherein when a main storage is to be accessed from a processor, a main storage protection is conducted by comparing by a comparator an access key output by said processor with a main storage key provided in the main storage, comprising: a first key register for storing a program status word key output by said processor; a second key register for storing an access key output by said processor in accordance with a data transfer instruction; a selector for selecting one of said first and second key register under control of said processor independently from storage access type; judging means coupled to said selector for judging whether a key selected by said selector is a predetermined value, allowing said processor to access said main storage irrespective of a value of said main storage key when the value of said selected key matches said predetermined value, and for comparing the value of said selected key to said main storage key; and pretesting means including a microprogram for executing a predetermined pretesting procedure, for setting said predetermined value in said second key register as a key for pretesting a data transfer between a plurality of address spaces when a key included in a transfer instruction coincides with said main storage key.

Claim 3

Dependent Claim 255 words

In an information processing apparatus wherein a plurality of address spaces produced by a plurality of address translation tables based on a selection command for a plurality of first address registers for holding first addresses of said plurality of address translation tables are accessed, and a program status word key and a storage key are compared by a comparator to protect a main storage, a multi-address space control system comprising: a first key register for holding said program status word key; a second key register for holding a work access key output by a processor in accordance with an instruction to be executed; a key selector for selecting one of said first and second key registers under control of said processor independently of storage access type; judging means coupled to the output of said key selector for judging whether the value of a key from said first key register or said second key register is a predetermined value, and allowing said processor to access said main storage irrespective of the output from said comparator when said key selected by said key selector is equal to said predetermined value; and pretesting means for pretesting access of address spaces by selecting one of said plurality of first address registers, and said first and second key registers, detecting an access exception, and storing, in response to an output from said comparator that an access exception is not detected, said predetermined value in said second key register as a key for use in transferring data between different address spaces.

Claim 4

Dependent Claim 255 words

In an information processing apparatus wherein a plurality of address spaces produced by a plurality of address translation tables based on a selection command for a plurality of first address registers for holding first addresses of said plurality of address translation tables are accessed, and a program status word key and a storage key are compared by a comparator to protect a main storage, a multi-address space control system comprising: a first key register for holding said program status word key; a second key register for holding a work access key output by a processor in accordance with an instruction to be executed; a key selector for selecting one of said first and second key registers under control of said processor independently of storage access type; judging means coupled to the output of said key selector for judging whether the value of a key from said first key register or said second key register is a predetermined value, and allowing said processor to access said main storage irrespective of the output from said comparator when said key selected by said key selector is equal to said predetermined value; and pretesting means for pretesting access of address spaces by selecting one of said plurality of first address registers, and said first and second key registers, detecting an access exception, and storing, in response to an output from said comparator that an access exception is not detected, said predetermined value in said second key register as a key for use in transferring data between different address spaces.

Claim 5

Dependent Claim 72 words

A system according to claim 2, wherein said instruction is a data transfer instruction having first and second operands, wherein one of said first and second operands is fetched and stored into an operand address, a key for said one of first and second operands is designated by said program status word key and a key for the other of the first and second operands is designated by said data transfer instruction.

Claim 6

Dependent Claim 30 words

A system according to claim 3, wherein said key selector selects one of said first and second key registers under control of a microprogram associated with said data transfer instruction.

Claim 7

Dependent Claim 56 words

A system according to claim 2, wherein said first key register holds key for detecting an access exception for one of first and second operands and said second key register holds a key given by a data transfer instruction as a key for detecting an access exception for the other of said first and second operands.

Claim 8

Dependent Claim 40 words

A system according to claim 2, wherein said second key register holds a key by which access to said main storage is permitted for transferring first and second operands of a predetermined until length through repetitive fetch and store operations.

Claim 9

Dependent Claim 255 words

A multi-address space control method for use in an information processing apparatus wherein a plurality of address spaces produced by a plurality of address translation tables based on a selection command for a plurality of first address registers for holding first addresses of said plurality of address translation tables are accessed, and a program status word key and a storage key are compared by a comparator to protect a main storage, said multi-address space control method comprising the steps of: (a) holding a first key register said program status word key; (b) holding in a second key register a work access key output by a processor in accordance with an instruction to be executed; (c) selecting by a key selector, one of said first and second key registers under control of said processor independently of storage access type; (d) judging whether the value of a key from said first key register or said second key register is a predetermined value, and allowing said processor to access said main storage irrespective of the output from said comparator when said key selected by said key selector is equal to said predetermined value; and (e) pretesting access of address spaces by selecting one of said plurality of first address registers, and said first and second key registers, detecting an access exception, and storing in response to an output from said comparator that an access exception is not detected, said predetermined value in said second key register as a key for use in transferring data between different address spaces.

Claim 10

Dependent Claim 255 words

A multi-address space control method for use in an information processing apparatus wherein a plurality of address spaces produced by a plurality of address translation tables based on a selection command for a plurality of first address registers for holding first addresses of said plurality of address translation tables are accessed, and a program status word key and a storage key are compared by a comparator to protect a main storage, said multi-address space control method comprising the steps of: (a) holding a first key register said program status word key; (b) holding in a second key register a work access key output by a processor in accordance with an instruction to be executed; (c) selecting by a key selector, one of said first and second key registers under control of said processor independently of storage access type; (d) judging whether the value of a key from said first key register or said second key register is a predetermined value, and allowing said processor to access said main storage irrespective of the output from said comparator when said key selected by said key selector is equal to said predetermined value; and (e) pretesting access of address spaces by selecting one of said plurality of first address registers, and said first and second key registers, detecting an access exception, and storing in response to an output from said comparator that an access exception is not detected, said predetermined value in said second key register as a key for use in transferring data between different address spaces.

Claim 11

Dependent Claim 72 words

A method according to claim 7, wherein said instruction is a data transfer instruction having first and second operands, wherein one of said first and second operands is fetched and stored into an operand address, a key for said one of first and second operands is designated by said program status word key and a key for the other of the first and second operands is designated by said data transfer instruction.

Claim 12

Dependent Claim 48 words

A method according to claim 7, wherein said step (b) comprises the steps of: holding in said second key register a key, by which access to said main storage is permitted, for transferring first and second operands of a predetermined until length through repetitive fetch and store operations.

Claim 13

Dependent Claim 39 words

A method according to claim 8, wherein said step (c) comprises the steps of: selecting, by said key selector selects one of said first and second key registers under control of a microprogram associated with said data transfer instruction.

Claim 14

Dependent Claim 66 words

A method according to claim 7, wherein said step (a) comprises the steps of: holding in said fist key register a key for detecting an access exception for one of first and second operands; and holding in said second key register a key given by a data transfer instruction as a key for detecting an access exception for the other of said first and second operands.

Claim 15

Dependent Claim 44 words

A method according to claim 7, wherein said step (e) includes a store pretesting step for pretesting an address space to which data is to be transferred and a fetch pretesting step for pretesting an address space from which data is to be transferred.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-03-11	1994-09-10	1995-03-12	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-03-11	1998-09-10	1999-03-12	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-03-11	2002-09-10	2003-03-12	$7700.00	Window Closed / Lapsed

Command controlled multi-storage space protection key pretesting system permitting access regardless of test result if selected key is predetermined value

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