Critical system protection

Claim 3

A method as defined in claim 1, the preventing step further comprising: interrupting the CPU execution of a program containing the instruction found by the sensing step to be fetched from a PF having an assigned TLB entry with the DO field position set to a DO page type state.

Claim 6

A method as defined in claim 3, the prohibiting step further comprising: interrupting the CPU execution of a program containing the instruction found by the sensing step to be fetched from a PF associated with a TLB entry containing a SENC field position set to a SENC state while the CPU is in a non-SCP state.

Claim 7

A method as defined in claim 3 or 4, further comprising: setting a system DO (data only) page flag in a PTE to a state which designates whether an associated virtual page contains only non-executable SCP data; setting a system DO field position in the assigned TLB entry to the state of the system DO page flag in the associated PTE; sensing (23) the state of the system DO field position in the assigned TLB entry for a requested virtual address of a store operand requested by an instruction being executed by the CPU; and disabling a storage access for the requested store operand when the sensing step senses the state of the system DO field position as a system DO page state, while the non-SCP state exists in the CPU, whereby the content of a system DO page type can only be changed by an instruction fetched from a SENC page type.

Claim 8

A method as defined in claim 5, the disabling step further comprising: interrupting the CPU execution of a program containing the instruction requesting the store operand when the disabling step is activated to prevent a store operation in the associated system DO page frame in main storage.

Claim 10

A method as defined in claim 7, further comprising: setting a pair of flag bit positions in each PTE to a page type code that represents the content of the associated virtual page to be one of: any data and/or program (any type), application (DO) data only, SENC program and/or data (SENC type), or system (DO) data only, whereby the application DO and system DO page types cannot contain any executable instructions.

Claim 11

A method as defined in claim 7 or 8, further comprising: initially setting the page type code in selected PTEs to represent SENC page types during an initial program loading of the page tables (9) for the system, and allocation setting of the system DO and eventually application DO page type codes in the PTEs for associated pages determined to contain a system DO page type or eventually an application DO page type when assigning each PF in main storage during the translating step.

Claim 12

A method as defined in claim 3 provided in a pipelined CPU, further comprising: selecting a TLB with a virtual address requested for an instruction fetch by the CPU; sensing (85) the SENC field position in the TLB entry selected by the selecting step; generating an instruction SENC signal with a state indicating a SENC or non-SENC page type according to the state sensed by the sensing step; buffering (95) each instruction SENC signal as an IS flag with each associated fetched instruction in an instruction buffer; registering (96) for execution an instruction from the instruction buffer with the associated IS flag; the resetting step resetting the SCP bistable device (117) to non-SCP state after the registering step if the IS flag indicates a non-SENC page type; and the prohibiting step suppressing the CPU execution of the instruction after the registering step when the IS flag indicates the instruction was fetched from a SENC page type and the CPU is not in SCP state.

Claim 13

Means for improving the integrity of virtual storage for a data processing system having a main storage, at least one CPU for accessing virtual pages in page frames (PFs) in main storage, the CPU capable of operating with dynamic address translation (DAT) for translating the virtual address of a page to a PF real address (PFRA) in main storage using a segment table and a page table (PT) in main storage, and a system control program (SCP) in the data processing system for controlling the resources of the system, characterized as: means setting a DO (data only) page flag in each PT entry (PTE) to a state which designates whether an associated virtual page contains only non-executable data, means setting a DO field position in the assigned TLB entry to the state of the DO page flag in the associated PTE, during each operation of translating a program requested virtual address and assigning an entry in a translation lookaside buffer (TLB) in the CPU to receive the address translation, including representations of the virtual address and a PFRA to locate the virtual page in main storage, means (28) sensing the state of the DO field position in the assigned TLB entry for a requested virtual address of each instruction fetch request by the CPU, and means preventing the CPU from completing execution of an instruction from a PF having an assigned TLB entry containing a DO field position sensed by the sensing means to have a state indicating a D0 page type.

Claim 14

Means for improving the integrity of virtual storage for a data processing system having a main storage, at least one CPU for accessing virtual pages in page frames (PFs) in main storage, the CPU capable of operating with dynamic address translation (DAT) for translating the virtual address of a page to a PF real address (PFRA) in main storage using a segment table and a page table (PT) in main storage, and a system control program (SCP) in the data processing system for controlling the resources of the system, characterized as: means setting a DO (data only) page flag in each PT entry (PTE) to a state which designates whether an associated virtual page contains only non-executable data, means setting a DO field position in the assigned TLB entry to the state of the DO page flag in the associated PTE, during each operation of translating a program requested virtual address and assigning an entry in a translation lookaside buffer (TLB) in the CPU to receive the address translation, including representations of the virtual address and a PFRA to locate the virtual page in main storage, means (28) sensing the state of the DO field position in the assigned TLB entry for a requested virtual address of each instruction fetch request by the CPU, and means preventing the CPU from completing execution of an instruction from a PF having an assigned TLB entry containing a DO field position sensed by the sensing means to have a state indicating a D0 page type.

Claim 15

Means for improving the integrity of virtual storage for a data processing system having a main storage, at least one CPU for accessing virtual pages in page frames (PFs) in main storage, the CPU capable of operating with dynamic address translation (DAT) for translating the virtual address of a page to a PF real address (PFRA) in main storage using a segment table and a page table (PT) in main storage, and a system control program (SCP) in the data processing system for controlling the resources of the system, characterized as: means (66) setting a SCP bistable device (17) when the CPU performs a hardware interrupt to designate that the CPU is in a SCP state; means setting a SENC (SCP executable non-changeable) page flag in each PT entry (PTE) (9) to a state which designates a SENC page type of content for an associated virtual page, in which the content can only be executed by a SCP program while the CPU is in SCP state and cannot be changed by a store request having a virtual address; means setting a SENC field position in the assigned TLB entry to the state of the SENC page flag in the associated PTE, assisting the means for translating a program requested virtual address and assigning a translation lookaside buffer (TLB) entry to receive the address translation, including representations of the virtual address and a PFRA to locate the virtual page in main storage; means (25) resetting the SCP bistable device to a non-SCP state when the CPU attempts to execute an instruction which is fetched from a PF associated with a PTE having the SENC page flag set to non-SENC state; means (27) sensing the state of the SENC field position in the assigned TLB entry for a requested virtual address of each instruction fetch request by the CPU; and means prohibiting the CPU from completing execution of an instruction from a PF having an assigned TLB entry containing a SENC field position set to a state indicating a SENC page type when the CPU is not in SCP state, whether or not the instruction is executing with the CPU in privileged state.

Claim 16

Means for improving the integrity of virtual storage for a data processing system having a main storage, at least one CPU for accessing virtual pages in page frames (PFs) in main storage, the CPU capable of operating with dynamic address translation (DAT) for translating the virtual address of a page to a PF real address (PFRA) in main storage using a segment table and a page table (PT) in main storage, and a system control program (SCP) in the data processing system for controlling the resources of the system, characterized as: means (66) setting a SCP bistable device (17) when the CPU performs a hardware interrupt to designate that the CPU is in a SCP state; means setting a SENC (SCP executable non-changeable) page flag in each PT entry (PTE) (9) to a state which designates a SENC page type of content for an associated virtual page, in which the content can only be executed by a SCP program while the CPU is in SCP state and cannot be changed by a store request having a virtual address; means setting a SENC field position in the assigned TLB entry to the state of the SENC page flag in the associated PTE, assisting the means for translating a program requested virtual address and assigning a translation lookaside buffer (TLB) entry to receive the address translation, including representations of the virtual address and a PFRA to locate the virtual page in main storage; means (25) resetting the SCP bistable device to a non-SCP state when the CPU attempts to execute an instruction which is fetched from a PF associated with a PTE having the SENC page flag set to non-SENC state; means (27) sensing the state of the SENC field position in the assigned TLB entry for a requested virtual address of each instruction fetch request by the CPU; and means prohibiting the CPU from completing execution of an instruction from a PF having an assigned TLB entry containing a SENC field position set to a state indicating a SENC page type when the CPU is not in SCP state, whether or not the instruction is executing with the CPU in privileged state.

Claim 17

Means as defined in claim 12, further comprising: means setting a system DO (data only) page flag in a PTE to a state which designates that an associated virtual page contains only non-executable SCP data, means setting a system DO field position in the assigned TLB entry to the state of the system DO page flag in the associated PTE, means sensing the state of the system DO field position in the assigned TLB entry for a requested virtual address of a store operand requested by an instruction being executed by the CPU, means (23) disabling a storage access for the requested store operand when the sensing means senses the state of the system DO field position as a system DO page state while the non-SCP state exists in the CPU, means interrupting the CPU execution of a program containing the ,instruction requesting the storage operand when the disabling means is activated to prevent a store operation in the associated system DO page frame in main storage, whereby the content of a system DO page type can only be changed by an instruction fetched from a SENC page type.

Claim 18

Means as defined in claim 13, further comprising: means setting one of separate SENC and system DO flag bit positions in each PTE to indicate the associated page is either a SENC page type or system DO page type, and means providing a system DO field position in each TLB to enable an indication to the CPU of a system DO page type having a content of system data only, whereby a system DO page type does not contain any executable instructions.

Claim 19

Means as defined in claim 13, further comprising: means setting a pair of flag bit positions in each PTE to a page type code that represents the content of the associated virtual page to be one of: any data and/or program (any type), application (DO) data only, SENC program and/or data (SENC type), or system (DO) data only, whereby the application DO and system DO page types cannot contain any executable instructions.