Integratable switched-capacitor sigma-delta modulator

Claim 2

Switched-capacitor sigma-delta modulator, comprising at least one memory element; at least one comparator connected to said at least one memory element; at least one integrator being connected to said at least one comparator; said at least one integrator having an input stage including a series circuit of a first switch, a first capacitor having two terminals and a second switch, a third switch for connecting one of the two terminals of said first capacitor to ground potential, and a fourth switch for connecting the other of the two terminals of said first capacitor to ground potential; a nodal point connected between said second and fourth switches and the other of the two terminals of said first capacitor; a negative feedback stage including second and third capacitors each having one terminal connected to said nodal point and each having another terminal, a fifth switch for connecting the other terminal of said second capacitor to a first potential, a sixth switch for connecting the other terminal of said third capacitor to a second potential, seventh and eighth series-connected switches for connecting the other terminal of said second capacitor to the second potential, and ninth and tenth series-connected switches for connecting the other terminal of said third capacitor to the first potential.

Claim 3

Sigma-delta modulator according to claim 1, wherein said first and second switches have switching phases opposed to said third and fourth switches, said fifth and sixth switches are triggered in phase, said seventh and ninth switches are switched in phase opposition to said first switch, and said eighth and tenth switches are triggered by the output signal of said memory element.

Claim 4

Switched-capacitor sigma-delta modulator, comprising at least one memory element supplying an output signal; at least one comparator connected to said at least one memory element; at least one integrator having differential inputs, being symmetrically wired and being connected to said at least one comparator; said at least one integrator having two input stages each including a series circuit of a first switch, a first capacitor with two terminals and a second switch, a third switch for connecting one of the two terminals of said first capacitor to ground potential, and a fourth switch for connecting the other of the two terminals of said first capacitor to ground potential; a first nodal point connected between said second and fourth switches and the other of the two terminals of said first capacitor of said first input stage, a second nodal point symmetrical to said first nodal point being connected between said second and fourth switches and the other of the two terminals of said first capacitor of said second input stage; a first negative feedback stage having a second capacitor with two terminals, a second negative feedback stage having a third capacitor with two terminals; a fifth switch for connecting one terminal of said second capacitor to said first nodal point, a sixth switch for connecting the one terminal of said second capacitor to said second nodal point, a seventh switch for connecting one terminal of said third capacitor to said first nodal point, an eighth switch for connecting the one terminal of said third capacitor to said second nodal point, each of said fifth, sixth, seventh and eighth switches operating as a function of the output signal of said memory element, a ninth switch for connecting the other terminal of said second capacitor to a first potential, a tenth switch for connecting the other terminal of said third capacitor to a second potential, an eleventh switch for connecting the other terminal of said second capacitor to the second potential, and a twelfth switch for connecting the other terminal of said third capacitor to the first potential.

Claim 5

Switched-capacitor sigma-delta modulator, comprising at least one memory element supplying an output signal; at least one comparator connected to said at least one memory element; at least one integrator having differential inputs, being symmetrically wired and being connected to said at least one comparator; said at least one integrator having two input stages each including a series circuit of a first switch, a first capacitor with two terminals and a second switch, a third switch for connecting one of the two terminals of said first capacitor to ground potential, and a fourth switch for connecting the other of the two terminals of said first capacitor to ground potential; a first nodal point connected between said second and fourth switches and the other of the two terminals of said first capacitor of said first input stage, a second nodal point symmetrical to said first nodal point being connected between said second and fourth switches and the other of the two terminals of said first capacitor of said second input stage; a first negative feedback stage having a second capacitor with two terminals, a second negative feedback stage having a third capacitor with two terminals; a fifth switch for connecting one terminal of said second capacitor to said first nodal point, a sixth switch for connecting the one terminal of said second capacitor to said second nodal point, a seventh switch for connecting one terminal of said third capacitor to said first nodal point, an eighth switch for connecting the one terminal of said third capacitor to said second nodal point, each of said fifth, sixth, seventh and eighth switches operating as a function of the output signal of said memory element, a ninth switch for connecting the other terminal of said second capacitor to a first potential, a tenth switch for connecting the other terminal of said third capacitor to a second potential, an eleventh switch for connecting the other terminal of said second capacitor to the second potential, and a twelfth switch for connecting the other terminal of said third capacitor to the first potential.

Claim 6

Sigma-delta modulator according to claim 2, wherein said first and second switches have switching phases opposed to said third and fourth switches, said ninth and tenth switches are triggered in phase, said eleventh and twelfth switches are switched in phase opposition to said first switch, and said fifth, sixth, seventh and eighth switches are triggered by the output signal of said memory element.