Patent US4999520A successfully refreshed from Google Patents.
US4999520A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed TTL buffer circuit which is resistive to the influence of alpha-rays
Assignee: Hitachi Ltd
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Filing: 1989-03-30
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Granted: 1991-03-12
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Expires: 2009-03-30
Abstract
Abstract A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.
Inventors
- 👤 Mitsuo Usami
- 👤 Noboru Shiozawa
- 👤 Toshio Yamada
- 👤 Hiromasa Katoh
- 👤 Kazuyoshi Satoh
- 👤 Tohru Kobayashi
- 👤 Tatsuya Kimura
- 👤 Masato Hamamoto
- 👤 Atsushi Shimizu
- 👤 Kaoru Koyu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K17/00; H03K17/04; H03K17/041; H03K17/0412; H03K17/04126; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K19/01; H03K19/013; H03K19/0136; H03K19/086
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
214 words
A semiconductor integrated circuit comprising: an inputting means for forming complementary first and second signals in accordance with an input signal supplied to an input terminal; a first voltage level outputting means for supplying an output signal of a first voltage level to an output terminal in accordance with the voltage level of said first signal; and a second voltage level outputting means for supplying temporarily an output signal of a second voltage level to said output terminal in accordance with said second signal formed by said inputting means depending on change of the voltage level of said input signal, wherein said inputting means comprises a first bipolar transistor in which a base is coupled to the input terminal, wherein said first voltage level outputting means comprises a second bipolar transistor forming an emitter follower in which a base is coupled to the collector of said first bipolar transistor, and an emitter to the output terminal, and wherein said second voltage level outputting means comprises a third bipolar transistor and a first capacitance, said third bipolar transistor having a collector coupled to the output terminal, having a base connected to a first electrode of said first capacitance, a second electrode of the first capacitance being coupled to the emitter of the first bipolar transistor.
Claim 2
Dependent Claim
214 words
A semiconductor integrated circuit comprising: an inputting means for forming complementary first and second signals in accordance with an input signal supplied to an input terminal; a first voltage level outputting means for supplying an output signal of a first voltage level to an output terminal in accordance with the voltage level of said first signal; and a second voltage level outputting means for supplying temporarily an output signal of a second voltage level to said output terminal in accordance with said second signal formed by said inputting means depending on change of the voltage level of said input signal, wherein said inputting means comprises a first bipolar transistor in which a base is coupled to the input terminal, wherein said first voltage level outputting means comprises a second bipolar transistor forming an emitter follower in which a base is coupled to the collector of said first bipolar transistor, and an emitter to the output terminal, and wherein said second voltage level outputting means comprises a third bipolar transistor and a first capacitance, said third bipolar transistor having a collector coupled to the output terminal, having a base connected to a first electrode of said first capacitance, a second electrode of the first capacitance being coupled to the emitter of the first bipolar transistor.
Claim 3
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 1, comprising a bias means for supplying a third signal of a third voltage level to the base of said third bipolar transistor.
Claim 4
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 3, wherein said bias means comprises a fourth bipolar transistor having an emitter coupled to the base of said third bipolar transistor and a base for receiving a fourth signal.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 3, wherein the collectors of said second and fourth bipolar transistors are formed in common on a semiconductor chip.
Claim 6
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 2, wherein said bias means comprises a resistance means coupled between the output terminal and the base of the third bipolar transistor.
Claim 7
Dependent Claim
35 words
A semiconductor integrated circuit according to claim 3, comprising a clamp means connected to the output terminal for keeping the voltage level of the output terminal to the level higher than a predetermined voltage level.
Claim 8
Dependent Claim
36 words
A semiconductor integrated circuit according to claim 6, wherein said clamp means comprises a fifth bipolar transistor in which an emitter is coupled to the output terminal and a fifth signal is supplied to a base.
Claim 9
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 7, wherein the collectors of said second, fourth and fifth bipolar transistors are formed in common on a semiconductor chip.
Claim 10
Dependent Claim
51 words
A semiconductor integrated circuit according to claim 1, further comprising a promoting means including the second capacitor, of which first electrode is coupled to a first electrode of first capacitor and second electrode to the output terminal, in order to promote the output operation of the second voltage level outputting means.
Claim 11
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 9, comprising a bias means for supplying a third signal of a third voltage level to the base of said third bipolar transistor.
Claim 12
Dependent Claim
40 words
A semiconductor integrated circuit according to claim 10, wherein said bias means comprises a fourth bipolar transistor in which an emitter is coupled to the base of said third bipolar transistor and a fourth signal is supplied to a base.
Claim 13
Dependent Claim
35 words
A semiconductor integrated circuit according to claim 11, comprising a clamp means coupled to the output terminal for keeping a voltage level of the output terminal to a level higher than a predetermined voltage level.
Claim 14
Dependent Claim
36 words
A semiconductor integrated circuit according to claim 12, wherein the clamp circuit includes the fifth bipolar transistor in which the emitter is coupled to the output terminal and the fifth signal is supplied to the base.
Claim 15
Dependent Claim
258 words
A semiconductor integrated circuit comprising: a logic means for supplying complementary first and second output signals to output terminals of first and second output terminals in response to an input signal; a first removing means which is coupled to said first output terminal to remove a voltage level of the first output terminal, a second removing means which is coupled to said second output terminal to remove a voltage level of the second output terminal, a first driving means which is coupled between said second output terminal and said first removing means and for creating a first signal to carry out removing operation of said first removing means when the second output signal supplied to the second output terminal changes to a second voltage level from a first voltage level, a second driving means which is coupled between the first output terminal and the second removing means and for creating a second signal to carry out removing operation of said second removing means when the first output signal supplied to the first output terminal changes to a second voltage le%el from a first voltage level, a first feedback means which is coupled between the first output terminal and the first removing means and for feeding back the first output signal supplied to the first output terminal to said first removing means, and a second feedback means which is coupled between the second output terminal and the first removing means and for feeding back the second output signal supplied to the second output terminal to said second removing means.
Claim 16
Dependent Claim
258 words
A semiconductor integrated circuit comprising: a logic means for supplying complementary first and second output signals to output terminals of first and second output terminals in response to an input signal; a first removing means which is coupled to said first output terminal to remove a voltage level of the first output terminal, a second removing means which is coupled to said second output terminal to remove a voltage level of the second output terminal, a first driving means which is coupled between said second output terminal and said first removing means and for creating a first signal to carry out removing operation of said first removing means when the second output signal supplied to the second output terminal changes to a second voltage level from a first voltage level, a second driving means which is coupled between the first output terminal and the second removing means and for creating a second signal to carry out removing operation of said second removing means when the first output signal supplied to the first output terminal changes to a second voltage le%el from a first voltage level, a first feedback means which is coupled between the first output terminal and the first removing means and for feeding back the first output signal supplied to the first output terminal to said first removing means, and a second feedback means which is coupled between the second output terminal and the first removing means and for feeding back the second output signal supplied to the second output terminal to said second removing means.
Claim 17
Dependent Claim
148 words
A semiconductor integrated circuit according to claim 14, wherein said logic means is an ECL logic circuit, said first removing means comprises a first bipolar transistor in which a collector is coupled to the first output terminal and a base to said first feedback means and said first driving means, said second removing means comprises a second bipolar transistor in which a collector is coupled to the second output terminal and a base to said second feedback means and said second driving means, said first driving circuit comprises a first capacitance in which a first electrode is coupled to the base of said first bipolar transistor and a second electrode to the second output terminal, and said second driving circuit comprises a second capacitance in which a first electrode is coupled to the base of said second bipolar transistor and a second electrode to the first output terminal.
Claim 18
Dependent Claim
55 words
A logic circuit according to claim 15, wherein said first feedback means comprises a first resistance means coupled between the first output terminal and the base of the first bipolar transistor and said second feedback means comprises a second resistance means coupled between the second output terminal and the base of the second bipolar transistor.
Claim 19
Dependent Claim
71 words
A logic circuit according to claim 15, wherein said first feedback means comprises a third bipolar transistor in which a base is coupled to the first output terminal and an emitter to the base of the first bipolar transistor, and said second feedback means comprises a fourth bipolar transistor in which a base is coupled to the second output terminal and an emitter to the base of the second bipolar transistor.
Claim 20
Dependent Claim
141 words
A plurality of unit circuits formed on a semiconductor chip having a plurality of electrodes, at least one unit circuit of said unit circuits comprising an input means for forming complementary first and second signals in accordance with an input signal supplied to an input terminal, a first voltage level outputting means for supplying an output signal of a first voltage level to an output terminal depending on a first voltage level signal, and a second voltage level outputting means for temporarily supplying an output signal of a second voltage level to the output terminal depending on the second signal created by the input means in accordance with change of voltage level of the power source voltage input signal, wherein at least one electrode among the plurality of electrodes is coupled to the power source voltage terminal of said unit circuit.
Claim 21
Dependent Claim
141 words
A plurality of unit circuits formed on a semiconductor chip having a plurality of electrodes, at least one unit circuit of said unit circuits comprising an input means for forming complementary first and second signals in accordance with an input signal supplied to an input terminal, a first voltage level outputting means for supplying an output signal of a first voltage level to an output terminal depending on a first voltage level signal, and a second voltage level outputting means for temporarily supplying an output signal of a second voltage level to the output terminal depending on the second signal created by the input means in accordance with change of voltage level of the power source voltage input signal, wherein at least one electrode among the plurality of electrodes is coupled to the power source voltage terminal of said unit circuit.
Claim 22
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 18, at least one unit circuit among the plurality of unit circuits is formed as a first capacitance.
Claim 23
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 19, second capacitances are formed between the plurality of unit circuits.
Claim 24
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 20, said semiconductor chip comprises a plurality of electrodes and is attached to the chip mounting carrier having a third capacitance formed therein.
Claim 25
Dependent Claim
136 words
A semiconductor integrated circuit comprising: a first bipolar transistor having a collector and an emitter at which complementary first and second signals are formed in accordance with an input signal supplied to a base; a second bipolar transistor having a base coupled to said collector of said first bipolar transistor and an emitter coupled to an output terminal; a third bipolar transistor having a base coupled to said emitter of said first bipolar transistor and a collector coupled to said output terminal; a first capacitor having a first electrode coupled to said emitter of said first bipolar transistor and a second electrode to said base of said third bipolar transistor; and first clamp means for keeping a voltage level of said base of said third bipolar transistor to a level higher than a predetermined voltage level.
Claim 26
Dependent Claim
136 words
A semiconductor integrated circuit comprising: a first bipolar transistor having a collector and an emitter at which complementary first and second signals are formed in accordance with an input signal supplied to a base; a second bipolar transistor having a base coupled to said collector of said first bipolar transistor and an emitter coupled to an output terminal; a third bipolar transistor having a base coupled to said emitter of said first bipolar transistor and a collector coupled to said output terminal; a first capacitor having a first electrode coupled to said emitter of said first bipolar transistor and a second electrode to said base of said third bipolar transistor; and first clamp means for keeping a voltage level of said base of said third bipolar transistor to a level higher than a predetermined voltage level.
Claim 27
Dependent Claim
65 words
A semiconductor integrated circuit according to claim 22, wherein said first clamp means comprises a fourth bipolar transistor having an emitter coupled to a common coupling node of said second electrode of said first capacitor and the base of said third bipolar transistor, having a collector coupled to a collector of said second bipolar transistor and having a base coupled to receive a third signal.
Claim 28
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 23, wherein said first clamp means comprises a first resistor coupled between said common coupling node and an emitter of said third bipolar transistor.
Claim 29
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 24, wherein said collector of said second bipolar transistor is coupled to a first power supply voltage terminal.
Claim 30
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 25, wherein said emitter of said third bipolar transistor is coupled to a second power supply voltage terminal.
Claim 31
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 26, further comprising a second resistor coupled between said collector of said first bipolar transistor and said first power supply voltage terminal.
Claim 32
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 27, further comprising a third resistor coupled between said emitter of said first bipolar transistor and said second power supply voltage terminal.
Claim 33
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 28, further comprising a second capacitor having a first electrode coupled to said output terminal and a second electrode coupled to said common coupling node.
Claim 34
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 29, further comprising a second clamp means coupled to said output terminal for keeping a voltage level of said output terminal to a level higher than a predetermined voltage level.
Claim 35
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 26, further comprising a second resistor coupled between said collector of said first bipolar transistor and a third power supply voltage terminal.
Claim 36
Dependent Claim
29 words
A semiconductor integrated circuit according to claim 31, further comprising a third resistor coupled between said emitter of said first bipolar transistor and a fourth power supply voltage terminal.
Claim 37
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 24, wherein said first capacitor comprises an isolation film formed between said first electrode and said second electrode.
Claim 38
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 29, wherein said second capacitor comprises an isolation film formed between said first electrode and said second electrode.
Claim 39
Dependent Claim
35 words
A semiconductor integrated circuit according to claim 28, further comprising a second capacitor having a first electrode coupled to said output terminal and a second electrode coupled to said base of said fourth bipolar transistor.
Claim 40
Dependent Claim
33 words
A semiconductor integrated circuit according to claim 35, further comprising a bias means coupled between said first power supply voltage terminal and said second power supply voltage terminal for forming said third signal.
Claim 41
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 36, wherein said bias means comprises a diode and a fourth resistor connected in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-11 | 1994-09-10 | 1995-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-11 | 1998-09-10 | 1999-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-11 | 2002-09-10 | 2003-03-12 | $7700.00 | Window Closed / Lapsed |