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US4998026A Expired / Lapsed US ⏱️ 0.0 years remaining

Driver circuit for in-circuit overdrive/functional tester

Assignee: HP Inc
•
Filing: 1989-04-19
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Granted: 1991-03-05
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Expires: 2009-04-19
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Abstract

Abstract A driver circuit for use in a circuit board tester which tester can perform both functional and in-circuit tests on a given device under test (DUT). The tester provides a test signal representative of a command for the driver circuit to provide logic high or logic low signals to a given device under test (DUT). The driver includes an output stage for providing desired logic high and logic low signals in response to the test signal; and switch circuitry, connected between the tester and the output stage, for preventing the test signal from reaching the output stage in response to a second control signal. The driver circuit is also shown to include an amplifier which, during operation of the driver circuit, receives feedback from the output stage. In addition, the driver circuit includes another output stage which provides a feedback signal when the driver circuit is in tri-state (deactivated). The driver circuit provides a low output impedance when logic high and logic low signals are being provided and a high output impedance when the driver circuit is in tri-state.

Inventors

  • 👤 Philip N. King

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 22:27
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/66; H03K17/665; H03K17/666; H03K17/667; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2806

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 195 words
A driver circuit for providing a test signal to a device under test, wherein said test signal is responsive to a combination of a predetermined logic signal and a control signal from a circuit board tester, said driver circuit comprising: a gain amplifier, having first and second input ports and at least one output port, for receiving said predetermined logic signal from said tester at said first input port and providing an output signal at said output port responsive to said predetermined logic signal and for receiving a feedback signal at said second input port; a first buffer, connected to receive said output signal, for generating a first feedback signal, said first buffer having a high output impedance; a second buffer, connected to receive said output signal and said control signal, for buffering said output signal and for providing said test signal, responsive to said output signal, to said device under test; and feedback means for providing a feedback signal to said second input port wherein said feedback signal comprises said first feedback signal when said test signal is representative of three-state and wherein said feedback signal comprises said test signal at all other times.
Claim 2
Dependent Claim 195 words
A driver circuit for providing a test signal to a device under test, wherein said test signal is responsive to a combination of a predetermined logic signal and a control signal from a circuit board tester, said driver circuit comprising: a gain amplifier, having first and second input ports and at least one output port, for receiving said predetermined logic signal from said tester at said first input port and providing an output signal at said output port responsive to said predetermined logic signal and for receiving a feedback signal at said second input port; a first buffer, connected to receive said output signal, for generating a first feedback signal, said first buffer having a high output impedance; a second buffer, connected to receive said output signal and said control signal, for buffering said output signal and for providing said test signal, responsive to said output signal, to said device under test; and feedback means for providing a feedback signal to said second input port wherein said feedback signal comprises said first feedback signal when said test signal is representative of three-state and wherein said feedback signal comprises said test signal at all other times.
Claim 3
Dependent Claim 32 words
The driver circuit of claim 1, wherein said feedback means comprises switch means for providing said test signal to said second input port when said driver circuit is not in said three-state.
Claim 4
Dependent Claim 42 words
The driver circuit of claim 2, wherein said switch means provides a low output impedance when said driver circuit is not in said tri-state and wherein said switch means provides a high output impedance when said driver circuit is in said three-state.
Claim 5
Dependent Claim 15 words
The driver circuit of claim 3, wherein said switch means comprises a field effect transistor.
Claim 6
Dependent Claim 25 words
The driver circuit of claim 1, wherein said first feedback signal prevents said gain amplifier from saturating when said driver circuit is in said three-state.

References Cited (Backward Citations)

US3781689A Cited
US3965468A Cited
US4588945A Cited
US4486674A Cited
US4612466A Cited
US4814638A Cited
US4800294A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-03-04 1994-09-03 1995-03-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-03-04 1998-09-03 1999-03-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-03-04 2002-09-03 2003-03-05 $7700.00 Window Closed / Lapsed

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