Disk drive clock writer

Claim 2

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: means for writing a preliminary clock pattern on the disk, said preliminary clock pattern having a number of clock pulses approximately equal to the predetermined number of clock pulses; and means for reading the preliminary clock pattern to verify the actual number of clock pulses; and means responsive to the reading means for writing a second clock pattern on the disk, which includes means for generating a source signal in phase with the preliminary clock pattern and correction means for advancing or retarding the phase of selected individual pulses of the source signal so that the second clock pattern has said predetermined number of clock pulses.

Claim 3

The disk drive clock writer of claim 1 further comprising: means for reading the second clock pattern; and means responsive to the second clock pattern reading means for writing a third clock pattern including means for reducing phase transients of the second clock pattern wherein the third clock pattern has said predetermined number of clock pulses.

Claim 6

The method of claim 3 further comprising: reading the second clock pattern; and writing a third clock pattern by for reducing phase transients of the second clock pattern wherein the third clock pattern has said predetermined number of clock pulses.

Claim 7

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: a signal source; means for generating a predetermined number of spaced correction pulses; and means responsive to the correction pulse means for writing a clock pattern on the disk, which includes means for advancing or retarding the phase of individual pulses of the source signal in response to correction pulses so that the clock pattern has said predetermined number of clock pulses.

Claim 8

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: a signal source; means for generating a predetermined number of spaced correction pulses; and means responsive to the correction pulse means for writing a clock pattern on the disk, which includes means for advancing or retarding the phase of individual pulses of the source signal in response to correction pulses so that the clock pattern has said predetermined number of clock pulses.

Claim 9

The disk drive clock writer of claim 5 wherein the correction pulse generating means comprises a counter and the writing means comprises a divider circuit.

Claim 10

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: a signal source; means for generating a predetermined number of spaced correction pulses; and means responsive to the correction pulse means for writing a clock pattern on the disk, which includes means for advancing or retarding the phase of individual pulses of the source signal in response to correction pulses so that the clock pattern has said predetermined number of clock pulses; wherein the correction pulse generating means comprises a counter and the writing means comprises a divider circuit; and wherein the divider circuit comprises a modulo counter state machine having a plurality of states in which the phase of the output of the divider circuit is advanced by skipping a state in response to an advance correction pulse and is retarded by repeating a state in response to a retard correction pulse.

Claim 11

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: a signal source; means for generating a predetermined number of spaced correction pulses; and means responsive to the correction pulse means for writing a clock pattern on the disk, which includes means for advancing or retarding the phase of individual pulses of the source signal in response to correction pulses so that the clock pattern has said predetermined number of clock pulses; wherein the correction pulse generating means comprises a counter and the writing means comprises a divider circuit; and wherein the divider circuit comprises a modulo counter state machine having a plurality of states in which the phase of the output of the divider circuit is advanced by skipping a state in response to an advance correction pulse and is retarded by repeating a state in response to a retard correction pulse.

Claim 12

The disk drive clock writer of claim 6 wherein the correction pulse generating means comprises a signal source, a second counter for counting the pulses of the signal source, and a second divider circuit coupled to the output of the second counter for dividing the frequency of the signal source, said second divider having means for advancing or retarding the phase of the second divider circuit output in response to the output of the second counter, the first counter being coupled to the output of the second divider circuit and the first divider circuit being coupled to the output of the first counter for dividing the frequency of the source signal, said first divider having means for advancing or retarding the phase of the first divider output in response to the output of the first counter.

Claim 13

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: a signal source; means for generating a predetermined number of spaced correction pulses; and a phase-locked loop which includes a voltage controlled oscillator, a divider having an input coupled to the output of the oscillator, and a phase detector having a first input coupled to the signal source and a second input coupled to the output of the divider, said divider including means for advancing or retarding the phase of individual pulses of the divider output in response to correction pulses so that the divider output has said predetermined number of clock pulses when written around a clock track.

Claim 14

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: a signal source; means for generating a predetermined number of spaced correction pulses; and a phase-locked loop which includes a voltage controlled oscillator, a divider having an input coupled to the output of the oscillator, and a phase detector having a first input coupled to the signal source and a second input coupled to the output of the divider, said divider including means for advancing or retarding the phase of individual pulses of the divider output in response to correction pulses so that the divider output has said predetermined number of clock pulses when written around a clock track.

Claim 15

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: an oscillator having a predetermined frequency; a phase lock loop circuit having an input coupled to the output of the oscillator for writing a preliminary clock pattern on the disk, said preliminary clock pattern having a number of clock pulses approximately equal to the predetermined number of clock pulses; means for reading the preliminary clock pattern to verify the actual number of clock pulses; and means responsive to the reading means for generating a predetermined number of phase advance or phase retard correction pulses as a function of the difference between the actual number of clock pulses in the preliminary clock pattern and the predetermined number of clock pulses; said phase lock loop circuit having an input coupled to the reading means to generate a source signal in phase with the preliminary clock pattern; wherein the clock writer further has correction means coupled to the output of the phase lock loop and responsive to the correction pulses for advancing or retarding the phase of selected individual pulses of the source signal so that the second cock pattern has said predetermined number of clock pulses, said correction means including a divider circuit comprising a modulo counter state machine having a plurality of states in which the phase of the output of the divider circuit is advanced by skipping a state in response to an advance correction pulse and is retarded by repeating a state in response to a retard correction pulse.

Claim 16

A disk drive clock writer for writing a clock pattern having a predetermined number of clock pulses around a clock track of a magnetic memory disk, comprising: an oscillator having a predetermined frequency; a phase lock loop circuit having an input coupled to the output of the oscillator for writing a preliminary clock pattern on the disk, said preliminary clock pattern having a number of clock pulses approximately equal to the predetermined number of clock pulses; means for reading the preliminary clock pattern to verify the actual number of clock pulses; and means responsive to the reading means for generating a predetermined number of phase advance or phase retard correction pulses as a function of the difference between the actual number of clock pulses in the preliminary clock pattern and the predetermined number of clock pulses; said phase lock loop circuit having an input coupled to the reading means to generate a source signal in phase with the preliminary clock pattern; wherein the clock writer further has correction means coupled to the output of the phase lock loop and responsive to the correction pulses for advancing or retarding the phase of selected individual pulses of the source signal so that the second cock pattern has said predetermined number of clock pulses, said correction means including a divider circuit comprising a modulo counter state machine having a plurality of states in which the phase of the output of the divider circuit is advanced by skipping a state in response to an advance correction pulse and is retarded by repeating a state in response to a retard correction pulse.