US3893172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic master clock track writer
Assignee: AG Communication Systems Corp
•
Filing: 1974-09-09
•
Granted: 1975-07-01
•
Expires: 1994-09-09
Abstract
Abstract A drum memory system of the type which includes a revolving magnetic drum adapted for the storage of data thereon has an automatic master clock track writer which assures that the drum index pulses stored on the drum for a single drum revolution are of a predetermined number and in a closed loop about the drum. The automatic master clock track writer or control circuit includes a pulse coincidence sensor for sensing when the last of the drum index pulses is coincident with a master reset pulse which marks the end of each drum revolution to detect when the drum index pulses are of the predetermined number and arranged on the drum in a closed loop. The control circuit additionally includes a function control means which sequentially causes the memory system erasing means, writing means and reading means to be enabled until the pulse coincidence sensor inhibits the erasing and writing means.
Inventors
- 👤 John Edward Celek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:00
CPC Classifications
G; G11; G11B; G11B5/00; G11B5/02; G11B5/09
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
365 words
In a drum memory system of the type which includes a revolving magnetic drum, a writing means including an index pulse source for providing the drum with index pulses until receipt of a count signal to afford ready access to data stored on the drum and a master reset pulse source for providing the drum with a reset pulse upon the completion of each drum revolution, reading means comprising an index pulse sensor for reading the index pulses on the drum and a reset pulse sensor for reading the reset pulses on the drum, an index pulse counter for counting the number of index pulses written onto and read from the drum and for providing the count signal when a predetermined number of index pulses have been counted, and an erasing means for erasing the index and reset pulses from the drum, the improvement of a control circuit for insuring that said predetermined number of index pulses are stored on the drum in a closed loop for a single drum revolution comprising: a first pulse coincidence sensing means coupled to said index pulse sensor and to said master reset pulse sensor for sensing the coincidence of an index pulse and a reset pulse and for providing a first control signal in response to such coincidence; a second pulse coincidence sensing means coupled to said first pulse coincidence sensing means and to said counter for providing a second control signal responsive to the coincidence of said first control signal and said count signal; and a latching means coupled to said second pulse coincidence sensing means for inhibiting said erasing and writing means and for providing an indication in response to said second control signal; whereby when a master reset pulse and an index pulse are coincident said first pulse coincidence sensing means provides said first control signal and when said first control signal is coincident with said count signal said second pulse coincidence sensing means provides said second control signal to cause said latching means to inhibit further erasing and writing and to provide an indication that the drum has recorded thereon for one drum revolution said predetermined number of index pulses in a closed loop.
Claim 2
Dependent Claim
365 words
In a drum memory system of the type which includes a revolving magnetic drum, a writing means including an index pulse source for providing the drum with index pulses until receipt of a count signal to afford ready access to data stored on the drum and a master reset pulse source for providing the drum with a reset pulse upon the completion of each drum revolution, reading means comprising an index pulse sensor for reading the index pulses on the drum and a reset pulse sensor for reading the reset pulses on the drum, an index pulse counter for counting the number of index pulses written onto and read from the drum and for providing the count signal when a predetermined number of index pulses have been counted, and an erasing means for erasing the index and reset pulses from the drum, the improvement of a control circuit for insuring that said predetermined number of index pulses are stored on the drum in a closed loop for a single drum revolution comprising: a first pulse coincidence sensing means coupled to said index pulse sensor and to said master reset pulse sensor for sensing the coincidence of an index pulse and a reset pulse and for providing a first control signal in response to such coincidence; a second pulse coincidence sensing means coupled to said first pulse coincidence sensing means and to said counter for providing a second control signal responsive to the coincidence of said first control signal and said count signal; and a latching means coupled to said second pulse coincidence sensing means for inhibiting said erasing and writing means and for providing an indication in response to said second control signal; whereby when a master reset pulse and an index pulse are coincident said first pulse coincidence sensing means provides said first control signal and when said first control signal is coincident with said count signal said second pulse coincidence sensing means provides said second control signal to cause said latching means to inhibit further erasing and writing and to provide an indication that the drum has recorded thereon for one drum revolution said predetermined number of index pulses in a closed loop.
Claim 3
Dependent Claim
45 words
A control circuit in accordance with claim 1 further comprising master reset pulse modifying means coupled between said reset pulse sensor and said first pulse coincidence sensing means for shortening the duration of the master reset pulses presented to said first pulse coincidence sensing means.
Claim 4
Dependent Claim
55 words
A control circuit in accordance with claim 2 wherein said master reset pulse modifying means comprises a first pulse shaper including a first delay network for delaying the leading edge of each reset pulse and a clamping circuit including a second delay network for terminating each said modified reset pulse after a predetermined time duration.
Claim 5
Dependent Claim
97 words
A control circuit in accordance with claim 2 wherein said first pulse coincidence sensing means comprises a flip-flop having a first input, a second input, a clock input, and an output, and an inverter having an input and an output, said first input being coupled to said master reset pulse modifying means, said second input being coupled to said inverter output, said inverter input also being coupled to said master reset pulse modifying means, said clock input being coupleD to said index pulse sensor, and said flip-flop output being coupled to said second pulse coincidence sensing means.
Claim 6
Dependent Claim
60 words
A control circuit in accordance with claim 2 wherein said second pulse coincidence sensing means comprises a NAND gate having a pair of inputs, one input being coupled to said first pulse coincidence sensing means, the other input being coupled to said index pulse counter for receiving said count signal therefrom, and said output being coupled to said latching circuit.
Claim 7
Dependent Claim
18 words
A control circuit in accordance with claim 2 wherein said latching circuit comprises a pair of NAND gates.
Claim 8
Dependent Claim
31 words
A control circuit in accordance with claim 1 further comprising an index pulse period increasing means coupled to said index pulse source for continuously increasing the period of said index pulses.
Claim 9
Dependent Claim
27 words
A control circuit in accordance with claim 7 wherein said pulse period increasing means further comprises a reset means to cause said drum to be initially underwritten.
Claim 10
Dependent Claim
100 words
A control circuit in accordance with claim 7 further comprising a function control means coupled to said erasing means, said writing means and said reading means, and coupled to said master reset pulse sensor for sequentially enabling said erasing means, said writing means, and said reading means responsive to first, second and third successive sets of reset pulses respectively, whereby said drum is sequentially erased, written with reset pulses and index pulses of continuously increasing periods and read until said second control signal is provided by said second pulse coincidence sensing means whereupon said erasing and writing means are inhibited.
Claim 11
Dependent Claim
17 words
A control circuit in accordance with claim 9 wherein said function control means comprises a ring counter.
Claim 12
Dependent Claim
42 words
A control circuit in accordance with claim 10 further comprising a flip-flop coupled between said ring counter and said master reset pulse sensor for dividing the frequency of said master reset pulses received by said ring counter by a factor of two.
Claim 13
Dependent Claim
69 words
A control circuit in accordance with claim 10 further comprising a gate and a latching circuit, said gate being coupled between said ring counter and said master reset pulse sensor, and said latching circuit being coupled to said ring counter and to said gate, and being responsive to said function control circuit enabling only said reading means for inhibiting said ring counter only when said reading means is enabled.
References Cited (Backward Citations)
US3531787A
Cited
US3668665A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |