US4995032A
Expired / Lapsed
US
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Label-switching and control interface for asynchronous fast-packet switching
Assignee: Telecom Italia SpA
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Filing: 1989-08-22
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Granted: 1991-02-19
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Expires: 2009-08-22
Abstract
Abstract A label-switching and control interface for asynchronous fast-packet switching consisting of a set of label-switching and cell-processing units controlled by a suitable control unit. The units operate at each multiplex level in real time thanks to a microprogrammed logic requiring the control processor intervention only at the connection set-up/release. The units implement the low levels of the flow control algorithms necessary to conveniently exploit the advantages of the techniques. The label becomes indicative of a virtual circuit which is allotted only locally to the call, annulling thus the necessity of very extensive labels, while the parameters which characterize the connection which uses a particular label are stored in the unit itself. Each unit switches the label characterizing the connection on the node input multiplex, with that whereby it is characterized on the output multiplex and at the same time associates, with each cell, the information necessary to multiplex switching which is then carried out in a self-routing network. The cells processed in this way by each unit of the set are statistically multiplexed in an asynchronous way and sent to a connection network termination. Such a termination serves a plurality of asynchronous multiplexes, which can be at a different frequency from each other and more particularly it is worth noting that each label-switching unit does not have its own operating frequency, but automatically takes up that of the asynchronous multiplex to which it is connected.
Inventors
- 👤 Carlo DeMichelis
- 👤 Paolo Mattone
- 👤 Alessandro Zappalorto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:37
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/20; H04L49/201; H04L49/203; H04J; H04J3/00; H04J3/24; H04J3/247
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
A label-switching and control interface for fast packet switching, comprising: a plurality of bidirectional asynchronus multiplex lines forwarding information-signal cells representing respective packets and corresponding to different calls; respective programmed-logic units connected to each of said bidirectional asynchronous multiplex lines for fast cell processing; a multiplex switching network having an input bus connected to all of said programmed-logic units; an arbitrating circuit between said input bus and said multiplex switching network and having a first bus connected therewith, said arbitrating circuit controlling communication between said programmed-logic units selectively and said multiplex switching network; a distribution circuit connected to all of said programmed-logic units by a second bus and to an output bus of said multiplex switching network; a common control circuit connected to all of said programmed-logic units by a third bus and accessing said multiplex switching network through a first connection to said arbitration circuit; and means forming a second connection between said distribution circuit and said control circuit whereby said multiplex switching network accesses said common control circuit.
Claim 2
Dependent Claim
170 words
A label-switching and control interface for fast packet switching, comprising: a plurality of bidirectional asynchronus multiplex lines forwarding information-signal cells representing respective packets and corresponding to different calls; respective programmed-logic units connected to each of said bidirectional asynchronous multiplex lines for fast cell processing; a multiplex switching network having an input bus connected to all of said programmed-logic units; an arbitrating circuit between said input bus and said multiplex switching network and having a first bus connected therewith, said arbitrating circuit controlling communication between said programmed-logic units selectively and said multiplex switching network; a distribution circuit connected to all of said programmed-logic units by a second bus and to an output bus of said multiplex switching network; a common control circuit connected to all of said programmed-logic units by a third bus and accessing said multiplex switching network through a first connection to said arbitration circuit; and means forming a second connection between said distribution circuit and said control circuit whereby said multiplex switching network accesses said common control circuit.
Claim 3
Dependent Claim
153 words
The label-switching and control interface as defined in claim 1 wherein each of said programmed logic units comprises an incoming section comprising: circuits detecting cell locations in a data flow along said lines; circuits separating datum cells from signalling, supervision, stuffing, auxiliary flow cells, carrying out label switching and adding self-routing code for the multiplex switching network; circuits for controlling the forwarding of cell octets to the multiplex switching network and for the temporary storage of a service class; circuits including a memory for storing cells for multipoint connections and for retransmission of the stored cells for a requested number of times; a further arbitrating circuit among sources of cells to be sent to the switching network; a processor; a temporary memory for cells intended for the processor and an interface for access to the memory by the processor; and an auxiliary output interface for emission of cells of an auxiliary information flow.
Claim 4
Dependent Claim
86 words
The label-switching and control interface defined in claim 2 wherein said programmed logic units each comprise a microprogrammed logic having: an arithmetic-logic unit with input and output registers connected to an internal bus through multiplexing and demultiplexing circuits; registers for particular operands connected to an output bus of the memory; a microprogrammed memory, a respective register and a sequencing circuit with a multiplexer for conditioned jumps and a multiplexer for bits under test; and a register for temporary storage of a label of a processed cell.
Claim 5
Dependent Claim
86 words
The label-switching and control interface defined in claim 2 wherein each of said programmed-logic units comprises a parallel interface for translating input cells into messages for the processor and processor messages into cells to transmit on a respective one of said lines, said parallel interface comprising: a control circuit for signalling the processor; a data register; a state register; a circuit for controlling an information flow coming from the processor; a further data register connected with the processor; and an addressing circuit controlled by the processor.
Claim 6
Dependent Claim
164 words
The label-switching and control interface defined in claim 4 wherein each of said blocks comprises a transmission section having: a temporary memory for the cells arriving from the further data registers; a temporary memory for the cells arriving from the multiplex switching network to be forwarded on the respective line, preceded by a circuit which selects cells meant for the respective unit and calculates label redundancies; a generator of stuffing cells and of supervision cells; control circuits for transmission and arbitration; and transmission circuits including a register for receiving octets of cells of an auxiliary flow, a register for receiving octets of the cells arriving from the processor through said temporary memory, a register for receiving supervision and stuffing cells arriving from said generator and a register for receiving the data cells arriving from the multiplex switching network through said temporary memory, a multiplexer for receiving the outputs of respective registers and a shift register for the transmission of octets on the respective line.
Claim 7
Dependent Claim
127 words
The label-switching and control interface defined in claim 2 wherein said arbitrating circuit comprises: logic circuits for receiving a request of forwarding the cells to the switching network by said programmed-logic units present and of the processor and the emission of corresponding enabling signals according to an arbitrating algorithm; a temporary memory circuit forming an interface between said processor and said multiplex switching network; a temporary memory circuit forming an interface between the switching network and the processor and for control of information flow from the network, and which unloads from the switching network cells not accepted by the programmed logic units or by the processor; and a converter for the conversion of the incoming and outgoing flows from parallel to series and from series to parallel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |