Far end echo cancellation method and apparatus

Claim 2

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, apparatus for reducing the effect of the far end echo signal at the receiver comprising quadrature detection and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal, receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and for using the receiver decision for generating an I and a Q error update signal, far end echo compensation circuitry responsive to said I and Q error update signals and a reference signal from the transmitter of the station for generating an I and a Q far end echo cancellation signal, means for combining said I echo cancellation signal and said I equalized receiver signal for generating said compensated I equalized receiver signal for delivery to said receiver decision circuitry, and means for combining said Q echo cancellation signal and said Q equalized receiver signal for generating said compensated Q equalized receiver signal for delivery to said receiver decision circuitry.

Claim 3

The apparatus of claim 1 wherein said far end echo compensation circuitry comprises a linear combination circuitry responsive to said I and Q error update signals and said reference signal for generating an I and Q unrotated echo canceler output signal, a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, and means, at said receiver decision circuitry, responsive to said compensated I and Q equalized signals for computing the rotation control update signal.

Claim 4

The apparatus of claim 1 wherein said I combining means and said Q combining means comprise an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry, and a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry, and said detection and equalization circuitry further comprises a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q error equalized receiver signals in response to a rotation control signal from the receiver decision circuitry.

Claim 5

The apparatus of claim 1 further comprising synchronization and amplitude circuitry for generating said reference signal as an amplitude interpolated signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals.

Claim 6

The apparatus of claim 4 wherein said synchronization and amplitude interpolation circuitry receives as its input discrete sample signals output by the transmitter at the baud rate of the transmitter, and has circuitry for providing said amplitude interpolated reference signal without converting the transmit signal to an analog signal and thereafter resampling a filtered version of the analog signal at the receiver clock rate.

Claim 7

The apparatus of claim 4 wherein said synchronization and interpolation circuitry comprises circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal at virtually any desired sampling phase or frequency corresponding to said clock signal for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate.

Claim 8

The apparatus of claim 6 wherein said synchronization and interpolation circuitry further comprises means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

Claim 9

The apparatus of claim 7 wherein said filtering and sampling circuitry comprises filter means having a span of at least twelve transmit baud periods.

Claim 10

The apparatus of claim 1 wherein said far end echo compensation circuitry comprises a linear combination circuitry responsive to rotation compensated I and Q error update signals and said reference signal for generating an I and Q unrotated echo canceler output signal, a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, an inverse rotation circuitry responsive to the phase locked loop rotation circuit for rotating the I and Q error update signals for providing said rotation compensated error update signals for updating said linear combination circuitry, and means, at said receiver decision circuitry, responsive to said compensated I and Q equalized signals for computing the rotation control update signal.

Claim 11

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, apparatus for reducing the effect of the far end echo signal at the receiver comprising quadrature decision and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal, receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and an I and a Q error update signal, far end echo compensation circuitry for generating an I and a Q far end echo cancellation signal including a linear combination circuitry responsive to said I and Q error update signals and a reference signal for generating an I and a Q unrotated echo canceler output signal, a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, and means, at the receiver decision circuitry, responsive to said compensated I and Q equalized signals, said I and Q cancellation signals, and said receiver decision, for computing the rotation control update signal, an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry, a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry, a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q equalized receiver signals in response to a rotation control signal from the receiver decision circuitry, and synchronization circuitry for generating said reference signal from said transmitter operating at a first clock rate and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals said synchronization circuitry including circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal corresponding to said transmit communications signal at a sample frequency corresponding to said receiver clock rate, and means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

Claim 12

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, apparatus for reducing the effect of the far end echo signal at the receiver comprising quadrature decision and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal, receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and an I and a Q error update signal, far end echo compensation circuitry for generating an I and a Q far end echo cancellation signal including a linear combination circuitry responsive to said I and Q error update signals and a reference signal for generating an I and a Q unrotated echo canceler output signal, a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, and means, at the receiver decision circuitry, responsive to said compensated I and Q equalized signals, said I and Q cancellation signals, and said receiver decision, for computing the rotation control update signal, an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry, a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry, a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q equalized receiver signals in response to a rotation control signal from the receiver decision circuitry, and synchronization circuitry for generating said reference signal from said transmitter operating at a first clock rate and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals said synchronization circuitry including circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal corresponding to said transmit communications signal at a sample frequency corresponding to said receiver clock rate, and means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

Claim 13

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, apparatus for reducing the effect of the far end echo signal at the receiver comprising quadrature decision and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal, receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and an I and a Q error update signal, far end echo compensation circuitry for generating an I and a Q far end echo cancellation signal including a linear combination circuitry responsive to rotation compensated I and Q error update signals and a reference signal for generating an I and a Q unrotated echo canceler output signal, a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, an inverse rotation circuitry responsive to the phase locked loop rotation circuit for rotating the I and Q error update signals for providing said rotation compensated error update signals for updating said linear combination circuitry, and means, at the receiver decision circuitry, responsive to said compensated I and Q equalized signals, said I and Q cancellation signals, and said receiver decision, for computing the rotation control update signal, an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry, a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry, a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q equalized receiver signals in response to a rotation control signal from the receiver decision circuitry, and synchronization circuitry for generating said reference signal from said transmitter operating at a first clock rate and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals said synchronization circuitry including circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal corresponding to said transmit communications signal at a sample frequency corresponding to said receiver clock rate, and means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

Claim 14

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, apparatus for reducing the effect of the far end echo signal at the receiver comprising quadrature decision and equalization circuitry for generating from a said received signal an I and a Q equalized receiver signal, receiver decision circuitry responsive to a compensated I and Q equalized receiver signal for generating a receiver decision and an I and a Q error update signal, far end echo compensation circuitry for generating an I and a Q far end echo cancellation signal including a linear combination circuitry responsive to rotation compensated I and Q error update signals and a reference signal for generating an I and a Q unrotated echo canceler output signal, a phase locked loop rotation circuit responsive to said I and Q unrotated canceler signals and to a rotation control update signal from the receiver decision circuitry for generating said I and Q far end echo cancellation signals, an inverse rotation circuitry responsive to the phase locked loop rotation circuit for rotating the I and Q error update signals for providing said rotation compensated error update signals for updating said linear combination circuitry, and means, at the receiver decision circuitry, responsive to said compensated I and Q equalized signals, said I and Q cancellation signals, and said receiver decision, for computing the rotation control update signal, an I summation circuitry for generating said compensated I receiver signal equal to a sum of said I cancellation signal and said I equalized receiver signal for delivery to said decision circuitry, a Q summation circuitry for generating said compensated Q receiver signal equal to a sum of said Q cancellation signal and said Q equalized receiver signal for delivery to said decision circuitry, a phase locked loop rotation circuitry for generating said I and Q equalized receiver signals from unrotated I and Q equalized receiver signals in response to a rotation control signal from the receiver decision circuitry, and synchronization circuitry for generating said reference signal from said transmitter operating at a first clock rate and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals said synchronization circuitry including circuitry responsive to the receiver clock signal for digitally filtering and sampling a transmitter output signal corresponding to said transmit communications signal at a sample frequency corresponding to said receiver clock rate, and means for interpolating between sample outputs of said filtering and sampling circuitry for providing a sampled value of said transmit signal as the reference signal in substantial synchronization with a receiver clock sample signal.

Claim 15

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, a method for reducing the effect of the far end echo signal at the receiver comprising the steps of quadrature detecting and equalizing the received signals for generating from said received signals and I and a Q equalized receiver signal, generating a receiver decision from a compensated I and Q equalized receiver signal, generating an I and a Q error update signal using the receiver decision and the compensated I and Q equalized receiver signal, generating an I and a Q far end echo cancellation signal in response to said I and Q error update signals and a reference signal from the transmitter of the station, combining said I echo cancellation signal and said I equalized receiver signal for generating said compensated I equalized receiver signal for delivery to a receiver decision circuitry, and combining said Q echo cancellation signal and said Q equalized receiver signal for generating said compensated Q equalized receiver signal for delivery to said receiver decision circuitry.

Claim 16

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, a method for reducing the effect of the far end echo signal at the receiver comprising the steps of quadrature detecting and equalizing the received signals for generating from said received signals and I and a Q equalized receiver signal, generating a receiver decision from a compensated I and Q equalized receiver signal, generating an I and a Q error update signal using the receiver decision and the compensated I and Q equalized receiver signal, generating an I and a Q far end echo cancellation signal in response to said I and Q error update signals and a reference signal from the transmitter of the station, combining said I echo cancellation signal and said I equalized receiver signal for generating said compensated I equalized receiver signal for delivery to a receiver decision circuitry, and combining said Q echo cancellation signal and said Q equalized receiver signal for generating said compensated Q equalized receiver signal for delivery to said receiver decision circuitry.

Claim 17

The method of claim 12 wherein said far end echo cancellation signal generating step comprises the steps of linearly combining samples of and said reference signal according to said I error update signal for generating an I linear combination output signal, linearly combining samples of said reference signal according to said Q error update signal for generating a Q linear combination output signal, rotating said I and Q linear combination signals in response to a phase error correction signal driving a phase rotation circuit for generating said I and Q far end echo cancellation signals, and generating the phase error correction for the next baud in response to the compensated I and Q equalized receiver signals, the rotated cancellation signals, and a receiver decision.

Claim 18

The method of claim 12 wherein said I combining step and said Q combining step comprise the steps of generating the sum of said I cancellation signal and said I equalized receiver signal, generating the sum of said Q cancellation signal and said Q equalized receiver signal, and generating said I and Q equalized receiver signals, using a phase locked loop rotation circuitry, in response to a rotation control signal from the receiver decision circuitry.

Claim 19

The method of claim 12 further comprising the step of generating said reference signal as an amplitude interpolated signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals.

Claim 20

The method of claim 15 wherein said interpolated reference signal generating step comprises the step of digitally filtering and sampling a transmitter output signal at virtually any desired sampling phase or frequency corresponding to said clock signal for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate.

Claim 21

The method of claim 16 wherein said generating step further comprises the step of interpolating between sample outputs from said filtering and sampling step for providing a sampled value of said transmit signal in substantial synchronization with said receiver clock signal.

Claim 22

The method of claim 17 wherein said filtering and sampling step comprises the step of providing a filter span extending over at least twelve transmit baud periods.

Claim 23

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, a method for reducing the effect of the far end echo signal at the receiver comprising the steps of quadrature detecting and equalizing the received signals for generating from said received signals an I and a Q equalized receiver signal, generating a receiver decision and an I and a Q error update signal from a compensated I and Q equalized receiver signal, linearly combining samples of said reference signal according to said I error update signal for generating an I linear combination output signal, linearly combining samples of said reference signal according to said Q error update signal for generating a Q linear combination output signal, rotating said I and Q linear combination signals in response to a phase error correction signal from a receiver decision step for generating said I and Q far end echo cancellation signals, generating said phase error correction for the next baud in response to the compensated I and Q equalized receiver signals, the rotated cancellation signals, and a receiver decision, generating the sum of said I cancellation signal and said I equalized receiver signal, generating the sum of said Q cancellation signal and said Q equalized receiver signal, generating said I and Q equalized receiver signals, using a phase locked loop rotation circuitry, in response to a rotation control signal from said receiver decision step, and generating said reference signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals, said reference signal generating step comprises the step of digitally filtering and sampling a transmitter output signal at a varying sampling phase and frequency corresponding to said clock signals for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate, and interpolating between sample outputs from said filtering and sampling step for providing a sampled value of said transmit signal in substantial synchronization with said receiver clock signal.

Claim 24

In a full duplex communications apparatus having at least two communicating modem stations, each station having a transmitter for placing transmit communications signals onto a two wire communications path, a receiver for receiving received communications signals from said communications path, and wherein each said received communications signal at a station has a noise-free signal component and a noise signal component, said noise signal component including a far end echo signal generated from said transmit signals of the station, a method for reducing the effect of the far end echo signal at the receiver comprising the steps of quadrature detecting and equalizing the received signals for generating from said received signals an I and a Q equalized receiver signal, generating a receiver decision and an I and a Q error update signal from a compensated I and Q equalized receiver signal, linearly combining samples of said reference signal according to said I error update signal for generating an I linear combination output signal, linearly combining samples of said reference signal according to said Q error update signal for generating a Q linear combination output signal, rotating said I and Q linear combination signals in response to a phase error correction signal from a receiver decision step for generating said I and Q far end echo cancellation signals, generating said phase error correction for the next baud in response to the compensated I and Q equalized receiver signals, the rotated cancellation signals, and a receiver decision, generating the sum of said I cancellation signal and said I equalized receiver signal, generating the sum of said Q cancellation signal and said Q equalized receiver signal, generating said I and Q equalized receiver signals, using a phase locked loop rotation circuitry, in response to a rotation control signal from said receiver decision step, and generating said reference signal from said transmitter operating at a first clock rate, and synchronized to said receiver operating at a receiver clock rate different than the first clock rate, said receiver clock rate being synchronized to the received communications signals, said reference signal generating step comprises the step of digitally filtering and sampling a transmitter output signal at a varying sampling phase and frequency corresponding to said clock signals for providing a sampled transmitter reference signal at a sample frequency corresponding to said receiver clock rate, and interpolating between sample outputs from said filtering and sampling step for providing a sampled value of said transmit signal in substantial synchronization with said receiver clock signal.