US4992985A
Expired / Lapsed
US
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Method for selectively initiating/terminating a test mode in an address multiplexed DRAM and address multiplexed DRAM having such a capability
Assignee: Hitachi Ltd
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Filing: 1989-03-07
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Granted: 1991-02-12
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Expires: 2009-03-07
Abstract
Abstract An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals with the write enable signal, which signal level combinations correspond to those which are otherwise left unused in the normal operating mode thereby obviating the requirement of an additional external control signal terminal. Such initiating of the test mode can be effected by setting the RAS signal of the DRAM at a logic "low" level when the CAS signal and the WE signal are at a logic "low" level. Clearing or resetting thereof is effected by the same combination sequence, except that the WE signal is at a logic "high" level. The setting or initiating of a test mode is also implemented by the additional combination of one of the row address signal bits, e.g. the most significant bit.
Inventors
- 👤 Kazuyuki Miyazawa
- 👤 Katsuhiro Shimohigashi
- 👤 Jun Etoh
- 👤 Katsutaka Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
102 words
A method of entering into a test mode from a normal operation mode in an address multiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal and a third external terminal for receiving a write enable signal, comprising the steps of: (a) setting said column address strobe signal at a logic "low" level; (b) setting said write enable signal at a logic "low" level; and (c) setting said row address strobe signal at a logic "low" level subsequent to said steps (a) and (b).
Claim 2
Independent Claim
102 words
A method of entering into a test mode from a normal operation mode in an address multiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal and a third external terminal for receiving a write enable signal, comprising the steps of: (a) setting said column address strobe signal at a logic "low" level; (b) setting said write enable signal at a logic "low" level; and (c) setting said row address strobe signal at a logic "low" level subsequent to said steps (a) and (b).
Claim 3
Dependent Claim
40 words
A method according to claim 1, further including the step of: (d) setting an address signal, received at a fourth external terminal of said dynamic RAM, at a predetermined logic level before the time wherein said step (c) is performed.
Claim 4
Dependent Claim
15 words
A method according to claim 2, wherein said address signal is a row address signal.
Claim 5
Dependent Claim
20 words
A method according to claim 3, wherein said row address signal is the most significant bit of a multi-bit address.
Claim 6
Dependent Claim
26 words
A method according to claim 4, wherein said most significant bit is an address A10 of an address including bits having an order of significance A1-A10.
Claim 7
Independent Claim
102 words
A method of returning to a normal operation state from a test mode in an address mutiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal and a third external terminal for receiving a write enable signal, comprising the steps of: (a) setting said column address strobe signal at a logic "low" level; (b) setting said write enable signal at a logic "high" level; and (c) setting said row address strobe signal at a logic "low" level subsequent to said steps (a) and (b).
Claim 8
Independent Claim
102 words
A method of returning to a normal operation state from a test mode in an address mutiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal and a third external terminal for receiving a write enable signal, comprising the steps of: (a) setting said column address strobe signal at a logic "low" level; (b) setting said write enable signal at a logic "high" level; and (c) setting said row address strobe signal at a logic "low" level subsequent to said steps (a) and (b).
Claim 9
Dependent Claim
40 words
A method according to claim 6, further including the step of: (d) setting an address signal, received at a fourth external terminal of said dynamic RAM, at a predetermined logic level before the time wherein said step (c) is performed.
Claim 10
Dependent Claim
15 words
A method according to claim 7, wherein said address signal is a row address signal.
Claim 11
Dependent Claim
20 words
A method according to claim 8, wherein said row address signal is the most significant bit of a multi-bit address.
Claim 12
Dependent Claim
26 words
A method according to claim 9, wherein said most significant bit is an address A10 of an address including bits having an order of significance A1-A10.
Claim 13
Independent Claim
136 words
A method of selecting one of test modes in an address multiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal and a fourth external terminal for receiving an address signal, comprising the steps of: (a) setting said column address strobe signal at a logic "low" level; (b) setting said write enable signal at a logic "low" level; (c) setting said row address strobe signal at a logic "low" level subsequent to said steps (a) and (b); and (d) designating a test mode for said dynamic RAM in response to said address signal being at a predetermined logic level at the time that said step (c) is performed.
Claim 14
Independent Claim
136 words
A method of selecting one of test modes in an address multiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal and a fourth external terminal for receiving an address signal, comprising the steps of: (a) setting said column address strobe signal at a logic "low" level; (b) setting said write enable signal at a logic "low" level; (c) setting said row address strobe signal at a logic "low" level subsequent to said steps (a) and (b); and (d) designating a test mode for said dynamic RAM in response to said address signal being at a predetermined logic level at the time that said step (c) is performed.
Claim 15
Dependent Claim
15 words
A method according to claim 11, wherein said address signal is a row address signal.
Claim 16
Dependent Claim
20 words
A method according to claim 12, wherein said row address signal is the most significant bit of a multi-bit address.
Claim 17
Dependent Claim
26 words
A method according to claim 13, wherein said most significant bit is an address A10 of an address including bits having an order of significance A1-A10.
Claim 18
Dependent Claim
97 words
An address multiplexed dynamic RAM having both a normal operational mode and a test mode comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; and a third external terminal for receiving a write enable signal, wherein said test mode is initiated in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 19
Dependent Claim
97 words
An address multiplexed dynamic RAM having both a normal operational mode and a test mode comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; and a third external terminal for receiving a write enable signal, wherein said test mode is initiated in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 20
Dependent Claim
68 words
An address multiplexed dynamic RAM according to claim 15, wherein said test mode is cleared and said dynamic RAM is returned to said normal operation state in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "high" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 21
Dependent Claim
123 words
An address multiplexed dynamic RAM having both a normal operational mode and a test mode comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and a fourth external terminal for receiving a first address signal and a second address signal, wherein said test mode is initiated in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said first address signal being at a first predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 22
Dependent Claim
123 words
An address multiplexed dynamic RAM having both a normal operational mode and a test mode comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and a fourth external terminal for receiving a first address signal and a second address signal, wherein said test mode is initiated in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said first address signal being at a first predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 23
Dependent Claim
86 words
An address multiplexed dynamic RAM according to claim 17, wherein said test mode is cleared and said dynamic RAM is returned to its normal operation state in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "high" level and said second address signal being at a second predetermined logic level, different from said first predetermined logic level, when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 24
Dependent Claim
28 words
An address multiplexed dynamic RAM according to claim 18, wherein said fourth external terminal is an address terminal for receiving the most significant bit of a multi-bit address.
Claim 25
Dependent Claim
31 words
An address multiplexed dynamic RAM according to claim 19, wherein said fourth external terminal receives the most significant bit A10 of an address including bits having an order of significance A1-A10.
Claim 26
Independent Claim
98 words
A method of entering into a test mode in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe (RAS) signal, a second external terminal for receiving a column address strobe (CAS) signal and a third external terminal for receiving a write enable signal, comprising the steps of: setting said CAS signal at a logic "low" level; setting said write enable signal at a logic "low" level; and setting said RAS signal at a logic "low" level when said CAS signal and said write enable signal are at a logic "low" level.
Claim 27
Independent Claim
98 words
A method of entering into a test mode in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe (RAS) signal, a second external terminal for receiving a column address strobe (CAS) signal and a third external terminal for receiving a write enable signal, comprising the steps of: setting said CAS signal at a logic "low" level; setting said write enable signal at a logic "low" level; and setting said RAS signal at a logic "low" level when said CAS signal and said write enable signal are at a logic "low" level.
Claim 28
Dependent Claim
46 words
A method according to claim 21, further including the step of: setting an address bit, received at a fourth external terminal of said dynamic RAM, at a predetermined logic level before the time wherein said step of setting said RAS signal at a logic "low" level.
Claim 29
Dependent Claim
15 words
A method according to claim 22, wherein said address bit is a row address bit.
Claim 30
Independent Claim
109 words
A method of returning to a normal operation state from a test mode in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe (RAS) signal, a second external terminal for receiving a column address strobe (CAS) signal and a third external terminal for receiving a write enable signal, comprising the steps of: setting said CAS signal at a logic "low" level; setting said write enable signal at a logic "high" level; and setting said RAS signal at a logic "low" level when said CAS signal is at a logic "low" level and said write enable signal is at a logic "high" level.
Claim 31
Independent Claim
109 words
A method of returning to a normal operation state from a test mode in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe (RAS) signal, a second external terminal for receiving a column address strobe (CAS) signal and a third external terminal for receiving a write enable signal, comprising the steps of: setting said CAS signal at a logic "low" level; setting said write enable signal at a logic "high" level; and setting said RAS signal at a logic "low" level when said CAS signal is at a logic "low" level and said write enable signal is at a logic "high" level.
Claim 32
Independent Claim
140 words
A method of selecting one of test modes in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe (RAS) signal, a second external for receiving a column address strobe (CAS) signal, a third external terminal for receiving a write enable signal and a fourth external terminal for receiving an address signal bit, comprising the steps of: setting said CAS signal at a logic "low" level; setting said write enable signal at a logic "low" level; and setting said RAS signal at a logic "low" level when said CAS signal and said write enable signal are at a logic "low" level designating a test mode in response to a predetermined logic state of said address bit at the time that said step of setting said RAS signal at a logic "low" level is effected.
Claim 33
Independent Claim
140 words
A method of selecting one of test modes in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe (RAS) signal, a second external for receiving a column address strobe (CAS) signal, a third external terminal for receiving a write enable signal and a fourth external terminal for receiving an address signal bit, comprising the steps of: setting said CAS signal at a logic "low" level; setting said write enable signal at a logic "low" level; and setting said RAS signal at a logic "low" level when said CAS signal and said write enable signal are at a logic "low" level designating a test mode in response to a predetermined logic state of said address bit at the time that said step of setting said RAS signal at a logic "low" level is effected.
Claim 34
Dependent Claim
16 words
A method according to claim 25, wherein said address signal bit is a row address bit.
Claim 35
Dependent Claim
22 words
A method according to claim 26, wherein said row address signal bit is the most significant bit of said row address signal.
Claim 36
Dependent Claim
89 words
An address multiplexed dynamic RAM having a normal operation mode and a test mode comprising: a first external terminal for receiving a row address strobe (RAS) signal; a second external terminal for receiving a column address strobe (CAS) signal; a third external terminal for receiving a write enable signal; and wherein said test mode is initiated in response to setting said RAS signal at a logic "low" level when said CAS signal is at a logic "low" level and said write enable signal is at a logic "low" level.
Claim 37
Dependent Claim
89 words
An address multiplexed dynamic RAM having a normal operation mode and a test mode comprising: a first external terminal for receiving a row address strobe (RAS) signal; a second external terminal for receiving a column address strobe (CAS) signal; a third external terminal for receiving a write enable signal; and wherein said test mode is initiated in response to setting said RAS signal at a logic "low" level when said CAS signal is at a logic "low" level and said write enable signal is at a logic "low" level.
Claim 38
Dependent Claim
48 words
An address multiplexed dynamic RAM according to claim 28, wherein said test mode is cleared in response to setting said RAS signal at a logic "low" level when said CAS signal is at a logic "low" level and said write enable signal is at a logic "high" level.
Claim 39
Dependent Claim
48 words
An address multiplexed dynamic RAM according to claim 28, wherein said test mode is cleared in response to setting said RAS signal at a logic "low" level when said CAS signal is at a logic "high" level and said write enable signal is at a logic "high" level.
Claim 40
Dependent Claim
55 words
An address multiplexed dynamic RAM according to claim 28, further comprising: a fourth external terminal for receiving an address bit, wherein one of test modes is selected based on the logic state of said address bit at the time that said test mode initiating sequence of said RAS, CAS and write enable signals is provided.
Claim 41
Dependent Claim
53 words
An address multiplexed dynamic RAM according to claim 28, further comprising: test means for writing data having the same value to the selected memory cells, verifying as to whether or not data which is read out of the selected memory cells are in agreement with predetermined data and providing a resultant verification output.
Claim 42
Dependent Claim
51 words
An address multiplexed dynamic RAM according to claim 32, said test means further comprising: selecting means for selecting multiple ones of said memory cells in accordance with an address signal which is synchronized with said RAS signal and in accordance with an address signal which is synchronized with said CAS signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-11 | 1994-08-13 | 1995-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-11 | 1998-08-13 | 1999-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-11 | 2002-08-13 | 2003-02-12 | $7700.00 | Window Closed / Lapsed |