US4992792A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital-analog converter for converting digital audio signals
Assignee: Alpine Electronics Inc
•
Filing: 1989-05-22
•
Granted: 1991-02-12
•
Expires: 2009-05-22
Abstract
Abstract A data generator generates digital data at a sampling time interval .sub.Δ T (sampling frequency f s =1/ΔT), and the three latest items of digital data V -1 , V 0 , V +1 are repeatedly latched successively in three latch circuits every 3·.sub.Δ T. A pulse response signal generator outputs unit pulse response signals of period 3·.sub.Δ T at the time interval ·.sub.Δ T, and three multiplying-type DA converters multiply these three unit pulse response signals φ 0 (t+.sub.Δ T), φ 0 (t), φ 0 (t-.sub.Δ T) by the digital data V -1 , V 0 , V +1 , respectively, at a speed of a·f s (a times in time .sub.Δ T). The outputs of these multiplying-type DA converters are combined into an analog signal S A , which is delivered as an output.
Inventors
- 👤 Ryoichi Mori
- 👤 Kazuo Toraichi
- 👤 Takashi Tokuyama
- 👤 Youichi Hashimoto
- 👤 Koichi Endo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:54
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/662
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
163 words
A digital-analog converter, comprising: a unit pulse response signal generator for successively generating unit pulse response signals, including first, second and third function generators, each unit pulse response signal having a period of 3·ΔT, successively delayed in phase by a predetermined time interval ΔT, where ΔT represents sampling time of digital data; a data generator for outputting an item of the digital data at the predetermined time interval; three memories, operatively connected to said data generator, for successively storing three latest items of the digital data output by said data generator; three multiplying-type digital/analog converters, each operatively connected to one of said first, second and third function generators and one of said three memories, for multiplying the unit pulse response signals by the digital data stored in said three memories, respectively and for outputting results of the multiplication as outputs; and a mixer for combining the outputs from said three multiplying-type digital/analog converters into an analog signal which is delivered as an output.
Claim 2
Dependent Claim
163 words
A digital-analog converter, comprising: a unit pulse response signal generator for successively generating unit pulse response signals, including first, second and third function generators, each unit pulse response signal having a period of 3·ΔT, successively delayed in phase by a predetermined time interval ΔT, where ΔT represents sampling time of digital data; a data generator for outputting an item of the digital data at the predetermined time interval; three memories, operatively connected to said data generator, for successively storing three latest items of the digital data output by said data generator; three multiplying-type digital/analog converters, each operatively connected to one of said first, second and third function generators and one of said three memories, for multiplying the unit pulse response signals by the digital data stored in said three memories, respectively and for outputting results of the multiplication as outputs; and a mixer for combining the outputs from said three multiplying-type digital/analog converters into an analog signal which is delivered as an output.
Claim 3
Dependent Claim
36 words
The digital-analog converter according to claim 1, wherein said first function generator generates the unit pulse response signal to produce a value of 0 at time t=0, 1 at time t=1.5·ΔT, and 0 at time t=3·ΔT.
Claim 4
Dependent Claim
44 words
The digital-analog converter according to claim 1, wherein said first function generator generates the unit pulse response signal to produce a value of 0 at time t=0, 0 at time t=0.5·ΔT, 1 at time t=1.5·ΔT, 0 at time t=2.5·ΔT and 0 at time t=3·ΔT.
Claim 5
Dependent Claim
52 words
The digital-analog converter according to claim 1, wherein said first function generator generates the unit pulse response signal to produce a value of 0 at time t=0, 0 at time t=0.5·ΔT, 0.5 at time t=ΔT, 1 at time t=1.5·ΔT, 0.5 at time t=2·ΔT, 0 at time t=2.5·ΔT, and 0 at time t=3.0·ΔT.
Claim 6
Dependent Claim
18 words
The digital-analog converter according to claim 4, wherein the unit pulse response signal is expressible by linear equations.
Claim 7
Dependent Claim
18 words
The digital-analog converter according to claim 4, wherein the unit pulse response signal is expressible by quadratic equations.
Claim 8
Dependent Claim
18 words
The digital-analog converter according to claim 4, wherein the unit pulse response signal is expressible by cubic equations.
Claim 9
Dependent Claim
34 words
The digital-analog converter according to claim 4, wherein the unit pulse response signal is expressible by a combination of curves including at least two of straight lines, cubic curves, sinusoidal curves and tangential curves.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-11 | 1994-08-13 | 1995-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-11 | 1998-08-13 | 1999-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-11 | 2002-08-13 | 2003-02-12 | $7700.00 | Window Closed / Lapsed |