US4992678A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed computer data transfer system
Assignee: Intellectual Ventures I LLC
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Filing: 1988-12-15
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Granted: 1991-02-12
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Expires: 2008-12-15
Abstract
Abstract A high speed computer data transfer system includes a clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.
Inventors
- 👤 Ikuo J. Sanwo
- 👤 Gregory H. Milby
- 👤 Moo Y. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
105 words
A high speed computer data transfer system for transferring digital data comprising: a data transfer bus; a pre-charger coupled to said bus for precharging said bus to a first logic level; a pulling circuit coupled to said bus for pulling said bus from said first logic level to a second logic level; and a clamping circuit coupled to said bus for preventing said bus from exceeding a threshold voltage during pre-charging, said clamping circuit providing a low impedance path from said bus to said threshold voltage when activated, whereby the time for transition from the first logic level to the second logic level is decreased.
Claim 2
Dependent Claim
105 words
A high speed computer data transfer system for transferring digital data comprising: a data transfer bus; a pre-charger coupled to said bus for precharging said bus to a first logic level; a pulling circuit coupled to said bus for pulling said bus from said first logic level to a second logic level; and a clamping circuit coupled to said bus for preventing said bus from exceeding a threshold voltage during pre-charging, said clamping circuit providing a low impedance path from said bus to said threshold voltage when activated, whereby the time for transition from the first logic level to the second logic level is decreased.
Claim 3
Dependent Claim
17 words
The data transfer system in claim 1 wherein said system is implemented using complementary metal-oxide-semiconductor (CMOS) technology.
Claim 4
Dependent Claim
56 words
The data transfer system in claim 2 wherein said clamping circuit comprises: a bias voltage setter for setting a bias voltage; and a clamping transistor coupled at its source to said bus and coupled at its gate to said bias voltage setter, said clamping transistor conducting when the voltage on said bus exceeds said bias voltage.
Claim 5
Dependent Claim
46 words
The data transfer system in claim 3 wherein pre-charging occurs only during pre-defined pre-charging intervals, and said clamping circuit further comprises: a clamping regulator transistor coupled to the drain of said clamping transistor, for conducting and hence allowing clamping to occur only during said pre-charging intervals.
Claim 6
Dependent Claim
21 words
The data transfer system in claim 3 wherein said bias voltage setter comprises two series coupled transistors of complementary conductivity type.
Claim 7
Dependent Claim
21 words
The data transfer system in claim 4 wherein said bias voltage setter comprises two series coupled transistors of complementary conductivity type.
Claim 8
Dependent Claim
29 words
The data transfer system in claim 1 further comprising a driver circuit coupled to said bus for inputting data in the form of logic high and logic low signals.
Claim 9
Dependent Claim
15 words
The data transfer system in claim 7 wherein said driver circuit comprises a CMOS switch.
Claim 10
Dependent Claim
31 words
The data transfer system in claim 1 further comprising a pre-charge control and delay circuit coupled to said pre-charger for activating said pre-charger after a current data transfer cycle is complete.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-11 | 1994-08-13 | 1995-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-11 | 1998-08-13 | 1999-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-11 | 2002-08-13 | 2003-02-12 | $7700.00 | Window Closed / Lapsed |