Patent US4991137A successfully refreshed from Google Patents.
US4991137A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Hitachi Ltd
•
Filing: 1989-12-11
•
Granted: 1991-02-05
•
Expires: 2009-12-11
Abstract
Abstract A semiconductor memory device is provided with memory cells which each comprises an insulated gate type field effect transistor and a capacitor connected in series with one another and connected to bit lines. The capacitor is composed of a pair of electrodes and a dielectric film which includes a silicon nitride film existing between the pair of electrodes. One electrode of the capacitor is provided with a terminal to which a voltage is applied. The value of the applied voltage is chosen so that the voltage applied between the pair of electrodes is smaller in an absolute value than a voltage applied to the bit line.
Inventors
- 👤 Tetsuro Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:55
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D84/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
315 words
A semiconductor memory device comprising: a first dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor coupled in series, said storage capacitor comprising a first electrode, a silicon nitride film, and a second electrode; a second dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor coupled in series, said storage capacitor comprising a first electrode, a silicon nitride film, and a second electrode; a first bit line which is coupled to one end of said series connection of said first dynamic memory cell; a second bit line which is coupled to one end of said series connection of said second dynamic memory cell; a differential amplifier means which is coupled to said first and second bit lines and which supplies a signal having one level of a predetermined high level and a predetermined low level to said first an second bit lines; a first terminal which is coupled to said differential amplifier means and which is supplied with a first reference voltage having a first level substantially identical with said predetermined high level; a second terminal which is coupled to said differential amplifier means and which is supplied with a second reference voltage having a second level substantially identical with said predetermined low level; and a third terminal which is coupled to the other ends of said series connections of said first and second dynamic memory cells and which supplies a voltage which is greater than said second level but less than said first level to said other ends of said series connections of said first and second dynamic memory cells so that a voltage of said storage capacitors of said first and second dynamic memory cells to be stored between said first electrode and said second electrode has a smaller absolute value than an absolute value of said first level.
Claim 2
Dependent Claim
315 words
A semiconductor memory device comprising: a first dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor coupled in series, said storage capacitor comprising a first electrode, a silicon nitride film, and a second electrode; a second dynamic memory cell which includes a series connection comprising a switching MISFET and a storage capacitor coupled in series, said storage capacitor comprising a first electrode, a silicon nitride film, and a second electrode; a first bit line which is coupled to one end of said series connection of said first dynamic memory cell; a second bit line which is coupled to one end of said series connection of said second dynamic memory cell; a differential amplifier means which is coupled to said first and second bit lines and which supplies a signal having one level of a predetermined high level and a predetermined low level to said first an second bit lines; a first terminal which is coupled to said differential amplifier means and which is supplied with a first reference voltage having a first level substantially identical with said predetermined high level; a second terminal which is coupled to said differential amplifier means and which is supplied with a second reference voltage having a second level substantially identical with said predetermined low level; and a third terminal which is coupled to the other ends of said series connections of said first and second dynamic memory cells and which supplies a voltage which is greater than said second level but less than said first level to said other ends of said series connections of said first and second dynamic memory cells so that a voltage of said storage capacitors of said first and second dynamic memory cells to be stored between said first electrode and said second electrode has a smaller absolute value than an absolute value of said first level.
Claim 3
Dependent Claim
23 words
A semiconductor memory device according to claim 1, further comprising a reference level supply means coupled to said first and second bit lines.
Claim 4
Dependent Claim
60 words
A semiconductor memory device according to claim 2, wherein said differential amplifier means includes means for generating complementary signals having said predetermined high level and said predetermined low level, respectively, in accordance with data stored in one of the first or second dynamic memory cells coupled to one of the first or second bit lines, respectively, and said reference level.
Claim 5
Dependent Claim
73 words
A semiconductor memory device according to claim 1, wherein said reference level supplying means comprises a first dummy cell coupled to said first bit lien and a second dummy cell coupled to said second bit line, each of said first and second dummy cells including a switching MISFET and a storage capacitor having a capacitance value which is less than capacitance values of said capacitors of said first and second dynamic memory cells.
Claim 6
Dependent Claim
44 words
A semiconductor memory device according to claim 4, wherein said storage capacitors of said first and second dummy cells each have a capacitance value which is one-half of the capacitance value of each of said capacitors of said first and second dynamic memory cells.
Claim 7
Dependent Claim
73 words
A semiconductor memory device according to claim 3, wherein said reference level supplying means comprises a first dummy cell coupled to said first bit line and a second dummy cell coupled to said second bit line, each of said first and second dummy cells including a switching MISFET and a storage capacitor having a capacitance value which is less than capacitance values of said capacitors of said first and second dynamic memory cells.
Claim 8
Dependent Claim
44 words
A semiconductor memory device according to claim 6, wherein said storage capacitors of said first and second dummy cells each have a capacitance value which is one-half of the capacitance value of each of said capacitors of said first and second dynamic memory cells.
References Cited (Backward Citations)
US4638460A
Cited
US4740920A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-04 | 1994-08-06 | 1995-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-04 | 1998-08-06 | 1999-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-04 | 2002-08-06 | 2003-02-05 | $7700.00 | Window Closed / Lapsed |