Cache memory addressable by both physical and virtual addresses

Claim 2

A cache memory system having, in combination: (a) a bus for receiving an address for desired data, said address having a plurality of bits including a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all corresponding virtual addressed and physical addressed data, (b) a data memory for storing system data, a switching element for transferring data from the data memory, (c) a tag memory having a virtual tag memory portion for storing the most significant bit portions of said virtual addresses associated with said stored data and a physical tag memory portion for storing the most significant bit portions of said physical addresses associated with said stored data, said stored virtual and physical most significant bit portions are addressed by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (d) address select means for selecting said stored virtual most significant bit portion when said received address is virtual and said stored physical most significant bit portion when said received address is physical; and (e) a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory.

Claim 3

The cache memory system of claim 1, and further comprising means for storing updated data in said data memory, the least significant bit portion of said updated data determining the address location in said data memory for storing said updated data; and means for storing the most significant bit portion of the associated physical and virtual address of said updated data in an address location in said tag memory determined by the least significant bit portion of the associated address of said updated data.

Claim 4

The cache memory of claim 1, wherein the least significant bit portion of the virtual and physical address associated with data is divided into first and second portions and said tag memory is divided into blocks of data, said first portion defining the address location of said blocks of data and said second portion defining the location of data within each of said blocks, said first portion of the least significant bit portion of the data address defining the location of said virtual and physical most significant bit portions of said stored data in said tag memory means.

Claim 5

The cache memory of claim 1, wherein said tag memory comprises first and second memory portions, each connected to the least significant bit portion of said bus and having a plurality of memory locations therein, each addressable by the least significant bit portion of said received address such that data is output from each of said first and second memory portions for a given least significant bit portion of said received address, said first memory portion storing most significant bit portions of the virtual address associated with data stored in said data memory and said second memory portion storing the most significant bit portion of the physical address associated with data stored in said data memory, addressing of said first and second memory portions simultaneously outputting the virtual and physical most significant bit portions of data corresponding to the least significant bit portion of the said received address.

Claim 6

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; address select means for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory; wherein said address select means comprises: an arbitration unit for receiving said address from said bus and determining whether said address is a virtual address or a physical address, said arbitration unit providing a control signal which identifies whether said received address is a virtual or physical address; and a multiplex switch interfaced with the output of said tag memory for selecting between said virtual most significant bit portion and said physical most significant bit portion output by said tag memory said multiplex switch controlled by said control signal from said arbitration unit to output said virtual most significant bit portion if said received address is virtual and said physical most significant bit portion if said received address is physical, the output of said multiplex switch being connected with the input of said comparator.

Claim 7

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; address select means for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory; wherein said address select means comprises: an arbitration unit for receiving said address from said bus and determining whether said address is a virtual address or a physical address, said arbitration unit providing a control signal which identifies whether said received address is a virtual or physical address; and a multiplex switch interfaced with the output of said tag memory for selecting between said virtual most significant bit portion and said physical most significant bit portion output by said tag memory said multiplex switch controlled by said control signal from said arbitration unit to output said virtual most significant bit portion if said received address is virtual and said physical most significant bit portion if said received address is physical, the output of said multiplex switch being connected with the input of said comparator.

Claim 8

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; address select means for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory; wherein said comparison means comprises an exclusive OR circuit for receiving the most significant bit portion of said received address and the most significant bit portion output by said address select means, the output of said exclusive OR circuit controlling said switch means when the most significant bit portion of said received address is identical to the most significant bit portion selected by said address select means.

Claim 9

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; address select means for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory; wherein said comparison means comprises an exclusive OR circuit for receiving the most significant bit portion of said received address and the most significant bit portion output by said address select means, the output of said exclusive OR circuit controlling said switch means when the most significant bit portion of said received address is identical to the most significant bit portion selected by said address select means.

Claim 10

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: (a) a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (b) address select means comprising an arbitration unit for receiving said address from said bus and determining whether said address is a virtual address or a physical address, said arbitration unit providing a control signal which identifies whether said received address is a virtual or physical address for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and (c) a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory.

Claim 11

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: (a) a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (b) address select means comprising an arbitration unit for receiving said address from said bus and determining whether said address is a virtual address or a physical address, said arbitration unit providing a control signal which identifies whether said received address is a virtual or physical address for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and (c) a comparison circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory.

Claim 12

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: (a) a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (b) address select means comprising an arbitration unit for receiving said address from said bus and determining whether said address is a virtual address or a physical address, said arbitration unit providing a control signal which identifies whether said received address is a virtual or physical address for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and (c) a multiplex switch interfaced with the output of said tag memory for selecting between said virtual most significant bit portion and said physical most significant bit portion output by said tag memory said multiplex switch controlled by said control signal from said arbitration unit to output said virtual most significant bit portion if said received address is virtual and said physical most significant bit portion if said received address is physical.

Claim 13

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: (a) a tag memory for storing the most significant bit portions of both virtual and physical addresses associated with said stored data, said stored virtual and physical most significant bit portions addressable by the least significant bit portion of said received address for output from said tag memory when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (b) address select means comprising an arbitration unit for receiving said address from said bus and determining whether said address is a virtual address or a physical address, said arbitration unit providing a control signal which identifies whether said received address is a virtual or physical address for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and (c) a multiplex switch interfaced with the output of said tag memory for selecting between said virtual most significant bit portion and said physical most significant bit portion output by said tag memory said multiplex switch controlled by said control signal from said arbitration unit to output said virtual most significant bit portion if said received address is virtual and said physical most significant bit portion if said received address is physical.

Claim 14

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (b) address select means for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and (c) a comparison circuit comprising logic circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory, said comparison circuit means for receiving the most significant bit portion of said received address and the most significant bit portion output by said address select means, the output of said logic circuit means controlling said switch means when the most significant bit portion of said received address is identical to the most significant bit portion selected by said address select means responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory.

Claim 15

A cache memory system having a bus for receiving an address for desired data, said address having a least significant bit portion comprised of a predetermined number of least significant bits and a most significant bit portion comprised of the remaining or most significant bits, the least significant bit portion of said address being common for all addressed data, a data memory for storing system data, and a switching element for transferring data from the data memory, further comprising: when said received least significant bit portion corresponds to the least significant bit portion of the said address associated with data stored in said data memory; (b) address select means for selecting said stored virtual most significant bit portion if said received address is virtual and said stored physical most significant bit portion if said received address is physical; and (c) a comparison circuit comprising logic circuit responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory, said comparison circuit means for receiving the most significant bit portion of said received address and the most significant bit portion output by said address select means, the output of said logic circuit means controlling said switch means when the most significant bit portion of said received address is identical to the most significant bit portion selected by said address select means responsive to said address select means for comparing said selected most significant bit portion to the most significant bit portion of said received address and providing an output to control said switching element for transfer of said selected data from said data memory.