Semiconductor capacitor

Claim 2

A capacitor comprising a first electrode; an insulator formed on said first electrode; and a second electrode formed on said insulator, wherein first and second semiconductor layers of p-type and n-type conductivity, respectively, are formed on the surface regions of said first and second electrodes at least on sides thereof adjacent to said insulator, said first and second semiconductor layers having an impurity doped concentration of 1×10 19 cm -3 to 2×10 21 cm -3 , wherein said insulator has a thickness of 2nm to 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected between said first and second electrodes, and wherein said first electrode is to be applied with a relatively positive bias voltage with respect to a reference at said second electrode.

Claim 3

A capacitor according to claim 1, wherein said semiconductor layers are composed of polycrystalline silicon.

Claim 4

A capacitor according to claim 1, wherein said first and second electrodes are vertically formed with said insulator being interposed therebetween, said first electrode is disposed beneath said second electrode and is also an impurity-doped region formed in an upper main surface region of a silicon substrate.

Claim 5

A capacitor according to claim 1, wherein said first and second electrodes are vertically formed with said insulator being disposed therebetween, said first electrode is disposed beneath said second electrode and is composed of a polycrystalline silicon film.

Claim 6

A capacitor according to claim 4, wherein said first electrode is electrically connected to an impurity-doped region, forming said first semiconductor layer, of a p-type conductivity that is formed in the surface region of said semiconductor substrate.

Claim 7

A semiconductor device comprising a capacitor formed on a semiconductor substrate to store data; and a MOS transistor for driving said capacitor, wherein said capacitor has a first electrode of one of a heavily doped p-type and n-type conductivity, electrically coupled to one of a source and drain of said MOS transistor, a second electrode of the other of said heavily doped p-type and n-type conductivity, and has a thin insulator interposed between said first electrode and said second electrode, wherein said insulator has a thickness of 2nm to 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected between said first and second electrodes, and wherein said first electrode corresponds to a storage node capacitance electrode and said second electrode is to be biased at a reference potential.

Claim 8

A semiconductor device comprising a capacitor formed on a semiconductor substrate to store data; and a MOS transistor for driving said capacitor, wherein said capacitor has a first electrode of one of a heavily doped p-type and n-type conductivity, electrically coupled to one of a source and drain of said MOS transistor, a second electrode of the other of said heavily doped p-type and n-type conductivity, and has a thin insulator interposed between said first electrode and said second electrode, wherein said insulator has a thickness of 2nm to 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected between said first and second electrodes, and wherein said first electrode corresponds to a storage node capacitance electrode and said second electrode is to be biased at a reference potential.

Claim 9

A semiconductor device according to claim 6, wherein said first and second electrodes are composed of silicon.

Claim 10

A semiconductor device according to claim 7, wherein said first and second electrodes are formed in a vertically stacked arrangement with said insulator being interposed therebetween, said first electrode is disposed beneath said second electrode and is also an impurity-doped region formed above an upper main surface region of said semiconductor substrate.

Claim 11

A semiconductor device according to claim 6, wherein said first and second electrodes are composed of polycrysatlline silicon films.

Claim 12

A semiconductor device according to claim 9, wherein said first and second electrodes have impurity concentrations of 1×10 19 cm -3 to 2×10 21 cm -3 at least on portions along sides thereof adjacent to said insulator.

Claim 13

A semiconductor device according to claim 9, wherein said capacitor is arranged on or over at least the gate of said MOS transistor, and said first electrode is electrically coupled to the source of said MOS transistor.

Claim 14

A capacitor according to claim 1, wherein at least said second of said semiconductor layers is comprised of polycrystalline silicon.

Claim 15

A semiconductor device according to claim 10, wherein said capacitor is arranged over at least a portion of the gate of said MOS transistor, and said first electrode is electrically coupled to the source of said MOS transistor.

Claim 16

A semiconductor device according to claim 13, wherein said first and second electrodes are of an n-type and p-type conductivity, respectively.

Claim 17

A semiconductor device according to claim 8, wherein said first and second electrodes are composed of polycrystalline silicon films.

Claim 18

A semiconductor device according to claim 15, wherein said capacitor is arranged over at least a portion of the gate of said MOS transistor, and said first electrode is electrically coupled to the source of said MOS transistor.

Claim 19

A semiconductor device according to claim 16, wherein said first and second electrodes are of an n-type and p-type conductivity, respectively.

Claim 20

A capacitor comprising a first electrode formed in an upper surface region of a silicon substrate; an insulator formed on said first electrode; and a second electrode formed on said insulator, wherein said first electrode and said second electrode include surface regions on sides thereof adjacent to said insulator of p-type and n-type conductivity, respectively, each surface region having an impurity-doping concentration of 1×10 19 cm -3 to 2×10 21 cm -3 , said second electrode including a polycrystalline silicon film, wherein said insulator has a thickness of not greater than 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected either directly or indirectly between said first and second electrodes, and wherein said first electrode is to be applied with a relatively positive bias voltage with respect to a reference at said second electrode.

Claim 21

A capacitor comprising a first electrode formed in an upper surface region of a silicon substrate; an insulator formed on said first electrode; and a second electrode formed on said insulator, wherein said first electrode and said second electrode include surface regions on sides thereof adjacent to said insulator of p-type and n-type conductivity, respectively, each surface region having an impurity-doping concentration of 1×10 19 cm -3 to 2×10 21 cm -3 , said second electrode including a polycrystalline silicon film, wherein said insulator has a thickness of not greater than 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected either directly or indirectly between said first and second electrodes, and wherein said first electrode is to be applied with a relatively positive bias voltage with respect to a reference at said second electrode.

Claim 22

A capacitor according to claim 18, wherein said insulator has a thickness of 2nm to 6nm in terms of a silicon dioxide equivalent.

Claim 23

A semiconductor device according to claim 18, wherein said positive bias voltage is less than 1.2 volts.

Claim 24

A semiconductor device according to claim 1, wherein said positive bias voltage is less than 1.2 volts.

Claim 25

A semiconductor device comprising a data storage capacitor formed on a semiconductor substrate; and a MOS transistor for driving said capacitor, wherein said capacitor has a first electrode of one of a p-type and n-type conductivity, electrically coupled to the source of said MOS transistor, a second electrode of the other of said p-type and n-type conductivity, and has an insulator interposed therebetween, wherein said insulator has a thickness of not greater than 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected, either directly or indirectly, between said first and second electrodes, wherein said first and second electrodes have impurity concentrations of 1×10 19 cm -3 to 2×10 21 cm -3 at least on portions along sides thereof adjacent to said insulator, and wherein said first electrode corresponds to a storage node capacitance electrode and said second electrode is to be biased at a reference potential.

Claim 26

A semiconductor device comprising a data storage capacitor formed on a semiconductor substrate; and a MOS transistor for driving said capacitor, wherein said capacitor has a first electrode of one of a p-type and n-type conductivity, electrically coupled to the source of said MOS transistor, a second electrode of the other of said p-type and n-type conductivity, and has an insulator interposed therebetween, wherein said insulator has a thickness of not greater than 6nm in terms of a silicon dioxide equivalent and is disposed such that a pn junction is not effected, either directly or indirectly, between said first and second electrodes, wherein said first and second electrodes have impurity concentrations of 1×10 19 cm -3 to 2×10 21 cm -3 at least on portions along sides thereof adjacent to said insulator, and wherein said first electrode corresponds to a storage node capacitance electrode and said second electrode is to be biased at a reference potential.

Claim 27

A capacitor according to claim 22, wherein said insulator has a thickness of 2nm to 6nm in terms of a silicon dioxide equivalent.