TTL to CMOS input buffer circuit

Claim 2

An input buffer circuit with compensation for device temperature change comprising: a first MOS transistor, of a first conduction type; a second MOS transistor, of a second conduction type; said first and second MOS transistors are serially connected by their current electrodes between a first power source and a second power source; an buffer input signal is applied to the gate of both said first and second MOS transistor, and a CMOS output signal is provided from a point of serial connection between said first and second MOS transistors; a third MOS transistor, of said first conduction type; said buffer input also being connected to the gate of said third MOS transistor; a switch switched by a signal indicating whether the device temperature is above or below a predetermined level; said third MOS transistor has a current electrode connected to said first power source, and another current electrode connected by said switch to the point of connection between said first MOS transistor and said second MOS transistor; whereby the logic threshold voltage level of the buffer is adjusted to provide temperature compensation.

Claim 3

A buffer circuit as recited in claim 1, wherein: said first conduction type is P channel; said second conduction type is N channel; and said switch is turned on when the device temperature increases to above said predetermined temperature level.

Claim 4

A buffer circuit as recited in claim 1, wherein: said first conduction type is N channel; said second conduction type is P channel; and said switch is turned on when the device temperature decreases to below said predetermined temperature level.

Claim 5

A buffer circuit as recited in claim 2, wherein: said first power source supplies Vcc; said second power source supplies Vss; and said first MOS transistor in said serial connection connects to said first power source and said second MOS transistor in said serial connection connects to said second power source.

Claim 6

A buffer circuit as recited in claim 3, wherein: said first power source supplies Vss; said second power source supplies Vcc; and said first MOS transistor in said serial connection connects to said first power source and said second MOS transistor in said serial connection connects to said second power source.

Claim 7

A buffer circuit as recited in claim 4, wherein: said switch is a P channel MOS transistor.

Claim 8

A buffer circuit as recited in claim 5, wherein: said switch is an N channel MOS transistor.

Claim 9

A buffer circuit as recited in claim 1, wherein: said signal switching said switch is generated by a circuit including a means for supplying current and a temperature sensitive resistor connected in series with said current supply means.

Claim 10

A buffer circuit as recited in claim 8, wherein: said circuit generating said switching signal further includes a means for converting an electrical signal at the point of connection between said current supply means and said temperature sensitive resistor to a digital signal constituting said switching signal for a corresponding switch.

Claim 11

A buffer circuit as recited in claim 9, wherein: said temperature sensitive resistor is made of polycrystalline silicon.

Claim 12

A buffer circuit as recited in claim 10, wherein: said converting means comprises two inverters connected in cascade.

Claim 13

A buffer circuit as recited in claim 10, wherein: said current supply means is a transistor set to operate in the subthreshold region.

Claim 14

A buffer circuit as recited in claim 12, wherein: said circuit generating said switching signal further includes a current setting means for setting the current supplied by said transistor constituting said current supply means.

Claim 15

A buffer circuit as recited in claim 13, wherein said current setting means provides an output to the gate electrode of said transistor constituting said current supply means and comprises: a first MOS transistor of one conduction type, which has a current electrode connected to a power source, a control electrode connected to another power source, and another current electrode connected to a first node; a second MOS transistor of another conduction type, which has a current electrode and a control electrode connected to said first node, and another current electrode connected to said another power source; said second MOS transistor has a sufficiently large geometric size relative to that of said first MOS transistor to have said second MOS transistor being operated in the subthreshold region; a third MOS transistor of said another conduction type, which has a control electrode connected to the control electrode of said second MOS transistor, a current electrode connected to said another power source, and another current electrode connected to a second node; said third MOS transistor has a geometric size smaller than that of said second MOS transistor; a fourth MOS transistor of said one conduction type, which has a first current electrode connected to said one power source, and a control electrode and another current electrode both connected to said second node; said fourth MOS transistor has a sufficiently large geometric size relative to that of said third MOS transistor to have said fourth MOS transistor being operated in the subthreshold region; and said output of the current setting means is provided from said second node.

Claim 16

An input buffer circuit with compensation for device temperature change comprising: a first MOS transistor, of a first conduction type; a second MOS transistor, of a second conduction type; said first and second MOS transistors are serially connected by their current electrodes between a first power source and a second power source; a buffer input signal is applied to the gate of both said first and second MOS transistor, and a CMOS output signal is provided from a point of serial connection between said first and second MOS transistors; a plurality of third MOS transistors, all being of said first conduction type; said buffer input also being connected to the gate of all said third MOS transistor; a plurality of switches, each being switched by a respective signal indicating whether the device temperature is above or below a different predetermined level; each said third MOS transistor has a current electrode connected to said first power source, and another current electrode connected by a corresponding one of said switches to the point of connection between said first MOS transistor and said second MOS transistor; whereby the logic threshold voltage level of the buffer is adjusted to provide temperature compensation.

Claim 17

An input buffer circuit with compensation for device temperature change comprising: a first MOS transistor, of a first conduction type; a second MOS transistor, of a second conduction type; said first and second MOS transistors are serially connected by their current electrodes between a first power source and a second power source; a buffer input signal is applied to the gate of both said first and second MOS transistor, and a CMOS output signal is provided from a point of serial connection between said first and second MOS transistors; a plurality of third MOS transistors, all being of said first conduction type; said buffer input also being connected to the gate of all said third MOS transistor; a plurality of switches, each being switched by a respective signal indicating whether the device temperature is above or below a different predetermined level; each said third MOS transistor has a current electrode connected to said first power source, and another current electrode connected by a corresponding one of said switches to the point of connection between said first MOS transistor and said second MOS transistor; whereby the logic threshold voltage level of the buffer is adjusted to provide temperature compensation.

Claim 18

A buffer circuit as recited in claim 15, wherein: said first conduction type is P channel; said second conduction type is N channel; and each of said switch is turned on when the device temperature increases to above a predetermined level as indicated by the associated switching signal of each said switch.

Claim 19

A buffer circuit as recited in claim 15 wherein: said first conduction type is N channel; said second conduction type is P channel; and each of said switch is turned on when the device temperature decreases to below a predetermined level as detected by the associated switching signal of each said switch.

Claim 20

A buffer circuit as recited in claim 16, wherein: said first power source supplies Vcc; said second power source supplies Vss; and said first MOS transistor in said serial connection connects to said first power source and said second MOS transistor in said serial connection connects to said second power source.

Claim 21

A buffer circuit as recited in claim 17, wherein: said first power source supplies Vss; said second power source supplies Vcc; and said first MOS transistor in said serial connection connects to said first power source and said second MOS transistor in said serial connection connects to said second power source.

Claim 22

A buffer circuit as recited in claim 18, wherein: each said switch is a P channel MOS transistor.

Claim 23

A buffer circuit as recited in claim 19, wherein: each said switch is an N channel MOS transistor.

Claim 24

A buffer circuit as recited in claim 15, wherein: each said switching signal switching an associated switch is generated by a respective circuit including a means for supplying current and a temperature sensitive resistor connected in series with said current supply means.

Claim 25

A buffer circuit as recited in claim 22, wherein: each of said circuit generating one of said switching signals and including a current supply means and a temperature sensitive resistor, further includes a means for converting an electrical signal at the point of connection between said current supply means and said temperature sensitive resistor to a digital signal constituting said switching signal for a corresponding switch.

Claim 26

A buffer circuit as recited in claim 23, wherein: each said current supply means supplies a different amount of current, whereby different switching signals correspond to different temperature levels.

Claim 27

A buffer circuit as recited in claim 23, wherein: each said temperature sensitive resistor has a resistance different from that of each other at the same temperature, whereby different switching signals correspond to different temperature levels.

Claim 28

A buffer circuit as recited in claim 24, wherein: said temperature sensitive resistor is made of polycrystalline silicon.

Claim 29

A buffer circuit as recited in claim 25, wherein: said temperature sensitive resistor is made of polycrystalline silicon.

Claim 30

A buffer circuit as recited in claim 26, wherein each said current supply means is a transistor set to operate in the subthreshold region, and has a different geometric size from each other.

Claim 31

A buffer circuit as recited in claim 27, wherein each said current supply means is a transistor set to operate in the subthreshold region.

Claim 32

A buffer circuit as recited in claim 28, wherein: each said transistor constituting a current supply means is set by a signal applied to its control electrode from a means for setting the current supplied by said current supply means.

Claim 33

A buffer circuit as recited in claim 29, wherein: each said transistor constituting a current supply means is set by a signal applied to its control electrode from a current setting means for setting the current supplied by said current supply means.

Claim 34

An input buffer circuit with compensation for device temperature change comprising: a first MOS transistor, of a first conduction type; a second MOS transistor, of a second conduction type; said first and second MOS transistors are serially connected by their current electrodes between a first power source and a second power source; a buffer input signal is applied to the gate of both said first and second MOS transistor, and a CMOS output signal is provided from a point of serial connection between said first and second MOS transistors; a third MOS transistor, of said first conduction type; said buffer input also being connected to the gate of said third MOS transistor; a first switch switched by a signal indicating whether the device temperature is above or below a first predetermined level; said third MOS transistor has a current electrode connected to said first power source, and another current electrode connected by said first switch to the point of connection between said first MOS transistor and said second MOS transistor; a fourth MOS transistor, of said second conduction type; said buffer input signal also being connected to the gate of said fourth MOS transistor; a second switch switched by a signal indicating whether the device temperature is above or below a second predetermined level; said fourth MOS transistor has a current electrode connected to said second power source, and another current electrode connected by said second switch to the point of connection between said first MOS transistor and said second MOS transistor; whereby the logic threshold voltage level of the buffer is adjusted to provide temperature compensation.

Claim 35

An input buffer circuit with compensation for device temperature change comprising: a first MOS transistor, of a first conduction type; a second MOS transistor, of a second conduction type; said first and second MOS transistors are serially connected by their current electrodes between a first power source and a second power source; a buffer input signal is applied to the gate of both said first and second MOS transistor, and a CMOS output signal is provided from a point of serial connection between said first and second MOS transistors; a third MOS transistor, of said first conduction type; said buffer input also being connected to the gate of said third MOS transistor; a first switch switched by a signal indicating whether the device temperature is above or below a first predetermined level; said third MOS transistor has a current electrode connected to said first power source, and another current electrode connected by said first switch to the point of connection between said first MOS transistor and said second MOS transistor; a fourth MOS transistor, of said second conduction type; said buffer input signal also being connected to the gate of said fourth MOS transistor; a second switch switched by a signal indicating whether the device temperature is above or below a second predetermined level; said fourth MOS transistor has a current electrode connected to said second power source, and another current electrode connected by said second switch to the point of connection between said first MOS transistor and said second MOS transistor; whereby the logic threshold voltage level of the buffer is adjusted to provide temperature compensation.

Claim 36

A buffer circuit as recited in claim 32, wherein: said first conduction type is P channel; said second conduction type is N channel; said first switch is turned on when the device temperature increases to above said first predetermined temperature level; and said second switch is turned on when the device temperature decreases to below said second predetermined temperature level.

Claim 37

A buffer circuit as recited in claim 33, wherein: said first power source supplies Vcc; said second power source supplies Vss; and said first MOS transistor in said serial connection connects to said first power source and said second MOS transistor in said serial connection connects to said second power source.

Claim 38

A buffer circuit as recited in claim 34, wherein: said first switch is a P channel MOS transistor.

Claim 39

A buffer circuit as recited in claim 35, wherein: said second switch is an N channel MOS transistor.

Claim 40

A buffer circuit as recited in claim 32, wherein: each said switching signal is generated by a circuit including a means for supplying current and a temperature sensitive resistor connected in series with said current supply means.

Claim 41

A buffer circuit as recited in claim 37, wherein: each of said circuit generating one of said switching signals and including a current supply means and a temperature sensitive resistor, further includes a means for converting an electrical signal at the point of connection between said current supply means and said temperature sensitive resistor to a digital signal constituting said switching signal for a corresponding switch.

Claim 42

A buffer circuit as recited in claim 38, wherein: said temperature sensitive resistor is made of polycrystalline silicon.

Claim 43

A buffer circuit as recited in claim 39, wherein each said current supply means is a transistor set to operate in the subthreshold region.

Claim 44

A buffer circuit as recited in claim 40, wherein: each said transistor constituting a current supply means is set by a signal applied to its control electrode from a current setting means for setting the current supplied by said current supply means.

Claim 45

A buffer circuit as recited in claim 41, wherein: each said transistor constituting a current supply means has a geometric size different from that of each other, whereby different switching signals correspond to different temperature levels.

Claim 46

A buffer circuit as recited in claim 41, wherein: each said temperature sensitive resistor has a resistance different from that of each other at the same temperature, whereby different switching signals correspond to different temperature levels.