US4988894A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power supply switching circuit
Assignee: Toshiba Corp
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Filing: 1989-06-14
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Granted: 1991-01-29
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Expires: 2009-06-14
Abstract
Abstract A power supply switching circuit includes first to third MOS transistors (P1, P2 and P3) connected in series between a high-potential source and a standard-potential source. The circuit performs a switching operation using a standard-potential and at least one potential which is different from the standard-poential, and outputs plural power supply potentials. The third MOS transistor (P3) is inserted between the first and second MOS transistors (P1 and P2). The back gate of the third transistor (P3) is connected to an output terminal (OUT1) formed between the second transistor (P2) and the third transistor (P3) and prevents the formation of a current path via turned-off transistor (P1) due to the action of a parasitic diode in the first and second transistors caused by potential fluctuations.
Inventors
- 👤 Akira Takiba
- 👤 Hiroyoshi Murata
- 👤 Yasoji Suzuki
- 👤 Isao Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:06
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/10; H03K17/102; H03K17/687; H03K17/693
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
209 words
A power supply switching circuit comprising: first, second, and third MOS transistors mutually connected in series such that said third MOS transistor is located between said first and second MOS transistors, wherein an output terminal is formed between said second MOS transistor and said third MOS transistor, and wherein a first potential is supplied to a source of said first MOS transistor and a standard potential is supplied to a drain of said second MOS transistor; an inverter having a pair of cooperative MOS transistors having sources through which a signal is outputted to a gate of said second MOS transistor in response to an input of said switching circuit; and a level shifter which outputs a low or high potential to said first MOS transistor in response to said input of said switching circuit; wherein a source of said third MOS transistor is connected to a drain of said first MOS transistor, a drain of said third MOS transistor is connected to a source of said second MOS transistor, and a back gate of said third MOS transistor is connected to said output terminal, said output terminal located at a connection point of said drain of said third MOS transistor to said source of said second MOS transistor.
Claim 2
Dependent Claim
209 words
A power supply switching circuit comprising: first, second, and third MOS transistors mutually connected in series such that said third MOS transistor is located between said first and second MOS transistors, wherein an output terminal is formed between said second MOS transistor and said third MOS transistor, and wherein a first potential is supplied to a source of said first MOS transistor and a standard potential is supplied to a drain of said second MOS transistor; an inverter having a pair of cooperative MOS transistors having sources through which a signal is outputted to a gate of said second MOS transistor in response to an input of said switching circuit; and a level shifter which outputs a low or high potential to said first MOS transistor in response to said input of said switching circuit; wherein a source of said third MOS transistor is connected to a drain of said first MOS transistor, a drain of said third MOS transistor is connected to a source of said second MOS transistor, and a back gate of said third MOS transistor is connected to said output terminal, said output terminal located at a connection point of said drain of said third MOS transistor to said source of said second MOS transistor.
Claim 3
Dependent Claim
35 words
A power supply switching circuit according to claim 1, wherein said first, second and third MOS transistors are p-channel transistors, and wherein a high potential is supplied to said source of said first MOS transistor.
Claim 4
Dependent Claim
35 words
A power supply switching circuit according to claim 1, wherein said first, second and third MOS transistors are n-channel transistors, and wherein a low potential is supplied to said source of said first MOS transistor.
Claim 5
Dependent Claim
23 words
A power supply switching circuit according to claim 1, wherein said input is applied to a gate electrode of said third MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-28 | 1994-07-30 | 1995-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-28 | 1998-07-30 | 1999-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-28 | 2002-07-30 | 2003-01-29 | $7700.00 | Window Closed / Lapsed |