Patent US4987560A successfully refreshed from Google Patents.
US4987560A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
•
Filing: 1989-03-27
•
Granted: 1991-01-22
•
Expires: 2009-03-27
Abstract
Abstract A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.
Inventors
- 👤 Takahiro Hamano
- 👤 Masataka Matsui
- 👤 Mitsuo Isobe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C29/00; G11C29/70; G11C29/78; G11C29/84; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; G11C8/00; G11C8/10; G11C8/20
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
372 words
A semiconductor memory device comprising a main memory cell array and a spare memory cell array, wherein each of the memory cell arrays includes a plurality of rows, each of which comprises a plurality of memory cells, each of which is identified by a row address signal corresponding to the row of the memory cell arrays in which each memory cell resides and by a column address signal corresponding to the column of the memory cell arrays in which each memory cell resides, and wherein the semiconductor memory device has a redundancy function for substituting a row of memory cells in said main memory cell array with a row of memory cells of said spare memory cell array when a one of the memory cells in the row of memory cells of said main memory cell array is defective, comprising: a plurality of main word lines to a respective one of which a plurality of memory cells arranged in a respective one of the rows of said main memory cell array are connected in parallel; and a main row decoder for receiving row address signals and for driving said plurality of main word lines, wherein during a data access period said main row decoder receives a row address signal and selectively drives a one of said plurality of main word lines in response to the received row address signal, and wherein said main row decoder comprises partial decoders, the number of which is equal to the number of said main word lines, and each of said partial decoders includes: a decoder for, during the data access period, receiving a row address signal; a drive circuit for driving a corresponding one of said plurality of main word lines in response to an output from said decoder; a fuse element inserted between an output terminal of said decoder and an input terminal of said drive circuit; and a MOS transistor having a source, drain and gate, a source-drain path being connected between an input terminal of said drive circuit and the predetermined potential, and means for applying a pulse signal to the gate to render the MOS transistor conductive when one of the memory cells connected to the corresponding main word line is defective.
Claim 2
Dependent Claim
372 words
A semiconductor memory device comprising a main memory cell array and a spare memory cell array, wherein each of the memory cell arrays includes a plurality of rows, each of which comprises a plurality of memory cells, each of which is identified by a row address signal corresponding to the row of the memory cell arrays in which each memory cell resides and by a column address signal corresponding to the column of the memory cell arrays in which each memory cell resides, and wherein the semiconductor memory device has a redundancy function for substituting a row of memory cells in said main memory cell array with a row of memory cells of said spare memory cell array when a one of the memory cells in the row of memory cells of said main memory cell array is defective, comprising: a plurality of main word lines to a respective one of which a plurality of memory cells arranged in a respective one of the rows of said main memory cell array are connected in parallel; and a main row decoder for receiving row address signals and for driving said plurality of main word lines, wherein during a data access period said main row decoder receives a row address signal and selectively drives a one of said plurality of main word lines in response to the received row address signal, and wherein said main row decoder comprises partial decoders, the number of which is equal to the number of said main word lines, and each of said partial decoders includes: a decoder for, during the data access period, receiving a row address signal; a drive circuit for driving a corresponding one of said plurality of main word lines in response to an output from said decoder; a fuse element inserted between an output terminal of said decoder and an input terminal of said drive circuit; and a MOS transistor having a source, drain and gate, a source-drain path being connected between an input terminal of said drive circuit and the predetermined potential, and means for applying a pulse signal to the gate to render the MOS transistor conductive when one of the memory cells connected to the corresponding main word line is defective.
Claim 3
Dependent Claim
22 words
The semiconductor memory device according to claim 1, wherein said drive circuit comprises an inverter for inverting an output from said decoder.
Claim 4
Dependent Claim
371 words
A semiconductor memory device comprising a main memory cell array and a spare memory cell array, wherein each of the memory cell arrays includes a plurality of rows, each of which comprises a plurality of memory cells, and wherein each memory cell is identified by a row address signal corresponding to the row of the memory cell arrays in which each memory cell resides and by a column address signal corresponding to the column of the memory cell arrays in which each memory cell resides, and wherein the semiconductor memory device has a redundancy function for substituting a row of memory cells in said main memory cell array with a row of memory cells of said spare memory cell array when a one of the memory cells in the row of memory cells of said main memory cell array is defective, comprising: a plurality of main word lines to a respective one of which a plurality of memory cells arranged in a respective one of the rows of said main memory cell array are connected in parallel; and a main row decoder for receiving row address signals and for driving said plurality of main word lines, wherein during a data access period the main row decoder receives a row address signal and selectively drives a one of said plurality of main word lines in responsive to the received row address signal, wherein said main row decoder comprises partial decoders, the number of which is equal to the number of said main word lines, and each of said partial decoders includes: a decoder for, during the data access period, receiving a row address signal; a drive circuit for driving a corresponding one of said plurality of main word lines in responsive to an output from said decoder; a fuse element inserted between an output terminal of said decoder and an input terminal of said terminal of said drive circuit; an MOS transistor having a source, drain and gate, a source-drain path being connected between the input terminal of said drive circuit and a predetermined potential; and means for applying a pulse signal to the gate of said MOS transistor during the data access period indicating non-selection of the row of memory cells.
Claim 5
Dependent Claim
371 words
A semiconductor memory device comprising a main memory cell array and a spare memory cell array, wherein each of the memory cell arrays includes a plurality of rows, each of which comprises a plurality of memory cells, and wherein each memory cell is identified by a row address signal corresponding to the row of the memory cell arrays in which each memory cell resides and by a column address signal corresponding to the column of the memory cell arrays in which each memory cell resides, and wherein the semiconductor memory device has a redundancy function for substituting a row of memory cells in said main memory cell array with a row of memory cells of said spare memory cell array when a one of the memory cells in the row of memory cells of said main memory cell array is defective, comprising: a plurality of main word lines to a respective one of which a plurality of memory cells arranged in a respective one of the rows of said main memory cell array are connected in parallel; and a main row decoder for receiving row address signals and for driving said plurality of main word lines, wherein during a data access period the main row decoder receives a row address signal and selectively drives a one of said plurality of main word lines in responsive to the received row address signal, wherein said main row decoder comprises partial decoders, the number of which is equal to the number of said main word lines, and each of said partial decoders includes: a decoder for, during the data access period, receiving a row address signal; a drive circuit for driving a corresponding one of said plurality of main word lines in responsive to an output from said decoder; a fuse element inserted between an output terminal of said decoder and an input terminal of said terminal of said drive circuit; an MOS transistor having a source, drain and gate, a source-drain path being connected between the input terminal of said drive circuit and a predetermined potential; and means for applying a pulse signal to the gate of said MOS transistor during the data access period indicating non-selection of the row of memory cells.
Claim 6
Dependent Claim
22 words
The semiconductor memory device according to claim 3, wherein said drive circuit comprises an inverter for inverting an output from said decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |