Patent US4987380A successfully refreshed from Google Patents.
US4987380A
Expired / Lapsed
US
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Gain controlled amplifier circuit
Assignee: Sanyo Electric Co Ltd
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Filing: 1989-08-07
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Granted: 1991-01-22
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Expires: 2009-08-07
Abstract
Abstract A gain controlled amplifier circuit includes a prior stage amplifier circuit (22) for amplifying an input signal, differentially connected first and second transistors (28, 29), and a current source transistor (27) connected to a common emitter of the first and the second transistors. An output current of the prior stage amplifier circuit is provided to the current source transistor, and a control signal is provided between bases of the first and the second transistors. A collector current of the second transistor is provided from an output terminal (31) as an output current, while a collector current of the first transistor is negatively fed back to the prior stage amplifier circuit through a negative feedback path (30).
Inventors
- 👤 Tsutomu Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:22
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3005; H03G1/00; H03G1/0005; H03G1/0017; H03G1/0023
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
256 words
A gain controlled amplifier circuit comprising: input means for providing an input signal; a prior stage amplifier circuit for amplifying said input signal, having a first input transistor having a base supplied with said input signal and providing a first output current from a collector and a second input transistor differentially connected to said first input transistor and providing a second output current from a collector; first and second transistors differentially connected to each other, each having a base, an emitter and a collector; third and fourth transistors differentially connected to each other, each having a base, an emitter and a collector; a fifth transistor having a base, an emitter and a collector, the collector of said fifth transistor being connected to the emitters connected in common of said first and second transistors, and the base of said fifth transistor being connected to the collector of said first input transistor; a sixth transistor having a base, an emitter and a collector, the collector of said sixth transistor being connected to the emitters connected in common of said third and fourth transistors, and the base of said sixth transistor being connected to the collector of said second input transistor; gain control means for providing a gain controlling signal to the bases of said first through fourth transistors; a negative feedback path for negative feeding back controller currents of said first and fourth transistors to the base of said second input transistor; and output terminals for providing collector currents of said second and third transistors as output signals.
Claim 2
Dependent Claim
256 words
A gain controlled amplifier circuit comprising: input means for providing an input signal; a prior stage amplifier circuit for amplifying said input signal, having a first input transistor having a base supplied with said input signal and providing a first output current from a collector and a second input transistor differentially connected to said first input transistor and providing a second output current from a collector; first and second transistors differentially connected to each other, each having a base, an emitter and a collector; third and fourth transistors differentially connected to each other, each having a base, an emitter and a collector; a fifth transistor having a base, an emitter and a collector, the collector of said fifth transistor being connected to the emitters connected in common of said first and second transistors, and the base of said fifth transistor being connected to the collector of said first input transistor; a sixth transistor having a base, an emitter and a collector, the collector of said sixth transistor being connected to the emitters connected in common of said third and fourth transistors, and the base of said sixth transistor being connected to the collector of said second input transistor; gain control means for providing a gain controlling signal to the bases of said first through fourth transistors; a negative feedback path for negative feeding back controller currents of said first and fourth transistors to the base of said second input transistor; and output terminals for providing collector currents of said second and third transistors as output signals.
Claim 3
Dependent Claim
91 words
A gain controlled amplifier circuit according to claim 1, further comprising: a seventh transistor having a collector and base connected in common to (a) the collector of said first input transistor and (b) the base of said fifth transistor; an eighth transistor having a collector and base connected in common to (c) the collector of said second input transistor and (d) the base of said sixth transistor; and said fifth and seventh transistors constituting a first current mirror circuit and said sixth and eighth transistors constituting a second current mirror circuit.
Claim 4
Dependent Claim
29 words
A gain controlled amplifier circuit according to claim 1, further comprising means for providing collector output currents of said second and third transistors in common to a load resistance.
Claim 5
Dependent Claim
74 words
A gain controlled amplifier circuit according to claim 3, wherein said prior stage amplifier circuit further includes, a first resistance connected between a reference power supply and the base of said first input transistor, a second resistance connected between the reference power supply and the base of said second input transistor, and the gain of the gain controlled amplifier being determined based on said load resistance, said second resistance and said gain controlling signal.
References Cited (Backward Citations)
US4379995A
Cited
US4516081A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |