Patent US4985831A successfully refreshed from Google Patents.
US4985831A
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Multiprocessor task scheduling system
Assignee: Evans and Sutherland Computer Corp
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Filing: 1988-10-31
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Granted: 1991-01-15
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Expires: 2008-10-31
Abstract
Abstract A task status word (TSW) is created for each task indicating, the instant location of the task, its priority and a record of synchronizing signals. Task status words are accessible from an addressable memory section for delivery to a TSW register. From the TSW register, a selected TSW effects control functions to synchronize tasks in different processors or computational units as well as input-output processors. A physical memory manager locates TSWs in response to signals, then checks the location of the task and the nature of the signal to determine signal routing to a processor. If a task is not in a processor, an interrupt manager resolves priority and signal significance indicated by the TSW to determine an interrupt.
Inventors
- 👤 Carole Dulong
- 👤 Jean-Yves Leclerc
- 👤 Patrick Scaglia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 10:54
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F9/4881
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
175 words
A task scheduling system for use to synchronize the execution of tasks in a multiprocessor, the multiprocessor cooperatively including a plurality of computational units, a memory, a control means and an input-output processor, and wherein tasks are initiated for execution in said multiprocessor and task signals involved in the execution of tasks are received and specified, said task scheduling system comprising: means operating in association with said memory for receiving and storing a plurality of task status words, said task status words identifying the status of certain of said task signals, and a present location of a task with respect to said multiprocessor, wherein said present location may comprise said memory or one of said computational units; task status word register means for selectively receiving task status words from said means for storing a plurality of task status words; and interpretative control means for supplying said task signals in said multiprocessor to specific locations in said multiprocessor for task synchronization under control of said task status word as stored in said task status word register.
Claim 2
Dependent Claim
175 words
A task scheduling system for use to synchronize the execution of tasks in a multiprocessor, the multiprocessor cooperatively including a plurality of computational units, a memory, a control means and an input-output processor, and wherein tasks are initiated for execution in said multiprocessor and task signals involved in the execution of tasks are received and specified, said task scheduling system comprising: means operating in association with said memory for receiving and storing a plurality of task status words, said task status words identifying the status of certain of said task signals, and a present location of a task with respect to said multiprocessor, wherein said present location may comprise said memory or one of said computational units; task status word register means for selectively receiving task status words from said means for storing a plurality of task status words; and interpretative control means for supplying said task signals in said multiprocessor to specific locations in said multiprocessor for task synchronization under control of said task status word as stored in said task status word register.
Claim 3
Dependent Claim
38 words
A system according to claim 1 wherein said interpretative control means further includes means for supplying a task signal to a specific computational unit under control of said task status word stored in said task status word register.
Claim 4
Dependent Claim
39 words
A system according to claim 1 wherein said interpretative control means further includes means for supplying a task signal to a specific location in memory under control of said task status word stored in said task status word register.
Claim 5
Dependent Claim
33 words
A system according to claim 1 wherein said task status words further identify a priority for the identified task and said interpretative control means supplies said task signals in accordance with said priority.
Claim 6
Dependent Claim
24 words
A system according to claim 4 further including a priority register means for storing the priority of tasks in process at said computational units.
Claim 7
Dependent Claim
47 words
A system according to claim 1 wherein said task status words further identify the priority of a task and the task signals pertinent for said task and certain of said task signals specify an interrupt, and wherein said interpretative means further effects interrupts for supplying task signals.
Claim 8
Dependent Claim
28 words
A system according to claim 6 wherein said interpretative means further includes a priority register means for storing the priority of tasks in process at said computational units.
Claim 9
Dependent Claim
136 words
A task scheduling process for use in a multiprocessor including a plurality of computational units, a memory, a control means and an input-output processor, and wherein tasks are initiated and task signals that are involved in the execution of tasks are specified, said process comprising the steps of: forming task status words for said tasks to indicate the status of certain of said task signals and the location of said tasks; registering said task status words to be addressable for access; receiving task signals, as from said input-output processor, for designated tasks; and selectively transferring said task signals to a designated task in accordance with a task status word for said designated task indicating the location of said designated task and the status of task signals for said designated task to thereby synchronize said designated task.
Claim 10
Dependent Claim
136 words
A task scheduling process for use in a multiprocessor including a plurality of computational units, a memory, a control means and an input-output processor, and wherein tasks are initiated and task signals that are involved in the execution of tasks are specified, said process comprising the steps of: forming task status words for said tasks to indicate the status of certain of said task signals and the location of said tasks; registering said task status words to be addressable for access; receiving task signals, as from said input-output processor, for designated tasks; and selectively transferring said task signals to a designated task in accordance with a task status word for said designated task indicating the location of said designated task and the status of task signals for said designated task to thereby synchronize said designated task.
Claim 11
Dependent Claim
45 words
A process according to claim 8 wherein the step of forming task status words further includes assigning priorities to said tasks and indicating said priorities in said task status words, and wherein said step of transferring said task signals is in accord with said priorities.
Claim 12
Dependent Claim
28 words
A process according to claim 9 further including a step of maintaining a schedule of priorities for said tasks for use in said step of transferring task signals.
Claim 13
Dependent Claim
49 words
A process according to claim 8 wherein the step of forming task status words further includes identifying task signals for said tasks and indicating said identified task signals in said task status words, and wherein said step of transferring said task signals is in accord with said task signals.
Claim 14
Dependent Claim
158 words
A multiprocessor system, comprising: a plurality of computational units; a memory, including a memory manager; a control system cooperatively coupled with said plurality of computational units and said memory for initiating and processing tasks by the utilization of task control signals; means operating in association with said memory for receiving and storing a plurality of task status words, said task status words identifying the status of certain of said task signals, and a present location of a task with respect to said multiprocessor, wherein said present location may comprise said memory or one of said computational units; a task status word register means for selectively receiving said task status words from said means for storing a plurality of task status words; and interpretive control means for supplying said task status signals in said multiprocessor to specific locations in said multiprocessor for task synchronization under control of said task status word as stored in said task status word register.
Claim 15
Dependent Claim
158 words
A multiprocessor system, comprising: a plurality of computational units; a memory, including a memory manager; a control system cooperatively coupled with said plurality of computational units and said memory for initiating and processing tasks by the utilization of task control signals; means operating in association with said memory for receiving and storing a plurality of task status words, said task status words identifying the status of certain of said task signals, and a present location of a task with respect to said multiprocessor, wherein said present location may comprise said memory or one of said computational units; a task status word register means for selectively receiving said task status words from said means for storing a plurality of task status words; and interpretive control means for supplying said task status signals in said multiprocessor to specific locations in said multiprocessor for task synchronization under control of said task status word as stored in said task status word register.
Claim 16
Dependent Claim
41 words
A multiprocessor system in accordance with claim 12 wherein said interpretive control means supplies said task signals in said multiprocessor to specific locations in accordance with the present location of the task and the status of certain of said task signals.
Claim 17
Dependent Claim
33 words
A microprocessor system according to claim 13 wherein said interpretive control means supplies said task signals in the event a task status word indicates a computational unit as the location of the task.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-14 | 1994-07-16 | 1995-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-14 | 1998-07-16 | 1999-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-14 | 2002-07-16 | 2003-01-15 | $7700.00 | Window Closed / Lapsed |