Patent US4984083A successfully refreshed from Google Patents.
US4984083A
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Image processing system
Assignee: Hitachi Ltd
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Filing: 1989-06-28
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Granted: 1991-01-08
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Expires: 2009-06-28
Abstract
Abstract An image processing system comprising a first and second video signal sources providing a main-field video signal and sub-field video signal, respectively, means for compressing the sub-field video signal on the time axis, and a signal merging unit which merges the compressed sub-field video signal into the main-field video signal and delivers the resulting signal to a television receiver set, wherein the signal compressing means comprising a dual-port memory having a first and second ports and operating to compress the sub-field video signal on the time axis and store the compressed signal, and control means for controlling the reading and writing of the memory for the sub-field video signal, the control means comprising a first control section for writing the sub-field video signal into the first port of said memory, a second control section for transferring a signal from the first port to the second port, and a third control section for reading out a signal from the second port, said memory implementing the reading operation and writing operation in asynchronous manner.
Inventors
- 👤 Kaneyuki Okamoto
- 👤 Hideo Nishijima
- 👤 Michio Masuda
- 👤 Hiroyasu Ohtsubo
- 👤 Koichi Ono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:46
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/44; H04N5/445; H04N5/45
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
150 words
An image processing system comprising: a memory which is capable of storing four fields of sub-field video signals; field discriminating means which discriminate odd-numbered and even-numbered fields of the sub-field video signals; divider means for diving the discriminated sub-field video signals; field discrimination means which discriminate odd-numbered and even-numbered fields of main-field video signals; displaying period control means which outputs a displaying period signal of the sub-field video signals; merging means which merges main-field video signals or sub-field video signals to output in accordance with the controlled displaying period signal; write address control means for deciding an address area in the memory to write information in accordance with the discriminated sub-field video signals and the divided sub-field video signals and; read address control means for deciding the read address area in the memory according to said discriminated main-field video signals, the displaying period signal and said divided sub-field video signals.
Claim 2
Dependent Claim
150 words
An image processing system comprising: a memory which is capable of storing four fields of sub-field video signals; field discriminating means which discriminate odd-numbered and even-numbered fields of the sub-field video signals; divider means for diving the discriminated sub-field video signals; field discrimination means which discriminate odd-numbered and even-numbered fields of main-field video signals; displaying period control means which outputs a displaying period signal of the sub-field video signals; merging means which merges main-field video signals or sub-field video signals to output in accordance with the controlled displaying period signal; write address control means for deciding an address area in the memory to write information in accordance with the discriminated sub-field video signals and the divided sub-field video signals and; read address control means for deciding the read address area in the memory according to said discriminated main-field video signals, the displaying period signal and said divided sub-field video signals.
Claim 3
Dependent Claim
121 words
An image processing system according to claim 1, wherein each of said field discriminating means for main-field and sub-field video signals comprises: a reversible counter which counts the number of horizontal sync signals inside or outside a vertical sync signal period of the image and sub-field video signals, means for presetting said reversible counter once in N periods (where N is a positive integer) of the vertical sync signal, sample-holding means which samples and holds the contents of said reversible counter immediately before presetting, second frequency-division means which implements frequency division for the vertical sync signal, and frequency-division phase control means which varies the frequency-division phase of said second frequency-division means in accordance with the output of said sample holding means.
Claim 4
Dependent Claim
68 words
An image processing system according to claim 2, further comprising: a counter for counting the vertical sync signal or the output of said second frequency-division means, variation detection means which detect whether or not the output of said sample-holding means varies during a certain count period of said counter, and means for operating on said frequency-division phase only at the detection of variation by said variation detecting means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-07 | 1994-07-09 | 1995-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-07 | 1998-07-09 | 1999-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-07 | 2002-07-09 | 2003-01-08 | $7700.00 | Window Closed / Lapsed |