Circuit for displaying picture of multiple channels

Claim 1

A circuit for displaying pictures of multiple channels, comprising: television-signal receiving means arranged to receive a television broadcasting signal and then to output a signal which has been subjected to video detection; a picture memory for storing signal information obtained by sequentially receiving broadcasting signals of a corresponding plurality of channels in a time-division fashion; synchronizing separator means for separating a synchronizing signal containing a horizontal synchronizing signal component from said video-detected signal; decision-making means for outputting a write enable signal and a decision signal representing a decision as to the presence of absence of each of said received broadcasting signals within said corresponding plurality of channels, said decision-making means utilizing said horizontal synchronizing signal component to thereby output said decision signal, said decision signal when output in the presence of said broadcasting signal differing from said decision signal when output in the absence of said broadcasting signal; picture memory controlling means for writing said signal information into said picture memory in response to said write enable signal, said picture memory controlling means including an address counter for providing access to said picture memory and means for generating a clock signal for use in said address counter, said means for generating said clock signal being responsive to said decision signal and generating a clock signal of first frequency to said address counter in the presence of said broadcasting signal and a clock signal of second frequency higher than said first frequency to said address counter in the absence of said broadcasting signal; and display means capable of displaying pictures of said plurality of channels on the basis of said signal information read from said picture memory.