US4983858A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Level determining circuit generating output signal at first or second output terminal according to level of input signal
Assignee: Sanyo Electric Co Ltd
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Filing: 1989-09-07
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Granted: 1991-01-08
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Expires: 2009-09-07
Abstract
Abstract A level determining circuit compares an input signal and a reference signal in level, generates a first output signal at a first output terminal (11) when the former is greater than the latter, and generates a second output signal at a second output terminal (12) if the former is smaller than the latter. A switch (15) is disposed in the preceding stage of the first output terminal, which will be opened if the first output signal is not required. A buffer amplifier portion (14) of high input impedance is further provided in the preceding stage of this switch so that the level determining operation can not be influenced by the change in impedance caused by switching of the switch.
Inventors
- 👤 Tsutomu Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:06
CPC Classifications
H; H03; H03G; H03G11/00; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2463; G; G01; G01R; G01R19/00; G01R19/165; G01R19/16566; G01R19/16576; H04; H04S; H04S7/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
230 words
A level determining circuit comprising: a reference voltage source (13), comparing means (1) for outputting a signal of one polarity in accordance with the relation of magnitude between two inputs, means (19) for supplying an input signal to one input of said comparing means therethrough, first and second rectifying means (2, 3) connected to the output of said comparing means to have the opposite polarities to each other, first and second feedback resistance means (4, 7) each for feeding back the output of said comparing means which has been rectified by said first or second rectifying means to the other input of said comparing means, means (8, 9, 18) for applying a reference voltage from said reference voltage source to each of the first node between said first rectifying means and said first feedback resistance means and the second node between said second rectifying means and said second feedback resistance means, first output terminal (11) for supplying a signal obtained at said first node therethrough, second output terminal (12) for supplying a signal obtained at said second node therethrough, buffer amplifier means (14) interposed in at least either one of the first signal path between said first node and said first output terminal and the second signal path between said second node and said second output terminal, and switch means (15) for disconnecting the output of said buffer amplifier means.
Claim 2
Dependent Claim
230 words
A level determining circuit comprising: a reference voltage source (13), comparing means (1) for outputting a signal of one polarity in accordance with the relation of magnitude between two inputs, means (19) for supplying an input signal to one input of said comparing means therethrough, first and second rectifying means (2, 3) connected to the output of said comparing means to have the opposite polarities to each other, first and second feedback resistance means (4, 7) each for feeding back the output of said comparing means which has been rectified by said first or second rectifying means to the other input of said comparing means, means (8, 9, 18) for applying a reference voltage from said reference voltage source to each of the first node between said first rectifying means and said first feedback resistance means and the second node between said second rectifying means and said second feedback resistance means, first output terminal (11) for supplying a signal obtained at said first node therethrough, second output terminal (12) for supplying a signal obtained at said second node therethrough, buffer amplifier means (14) interposed in at least either one of the first signal path between said first node and said first output terminal and the second signal path between said second node and said second output terminal, and switch means (15) for disconnecting the output of said buffer amplifier means.
Claim 3
Dependent Claim
24 words
The level determining circuit according to claim 1, which further comprises resistance means for dividing voltage of the output of said buffer amplifier means.
Claim 4
Dependent Claim
43 words
The level determining circuit according to claim 1, wherein said comparing means generates a positive output signal when said input signal is greater than said reference signal, and generates a negative output signal when said input signal is smaller than said reference signal.
Claim 5
Dependent Claim
17 words
The level determining circuit according to claim 1, wherein said first and second rectifying means comprise diodes.
Claim 6
Dependent Claim
52 words
The level determining circuit according to claim 1, wherein said reference voltage applying means comprises first resistance means for applying said reference voltage to said first node, and second resistance means for applying said reference voltage to said second node, and said first and second resistance means having the same resistance values.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-07 | 1994-07-09 | 1995-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-07 | 1998-07-09 | 1999-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-07 | 2002-07-09 | 2003-01-08 | $7700.00 | Window Closed / Lapsed |