US4982194A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Back-sampling charge redistribution analog to digital converter
Assignee: Intersil Corp
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Filing: 1989-04-20
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Granted: 1991-01-01
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Expires: 2009-04-20
Abstract
Abstract Aperture delay and jitter are reduced when the sequence of operation of a charge redistribution analog to digital converter is arranged so that signal acquisition occurs in the idle time of the converter. Conversion begins by terminating the acquisition or sample phase immediately upon receipt of the start conversion command. Approximation begins directly thereafter. Upon completion of the successive approximation conversion phase and latching the result the capacitor array is discharged. The comparator offset is sampled and held and the acquisition phase is initiated and continues until receipt or occurrence of the next start conversion command.
Inventors
- 👤 Kantilal Bacrania
- 👤 Chong I. Chi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:52
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/0836; H03M1/12; H03M1/34; H03M1/38; H03M1/46; H03M1/466; H03M1/468; H03M1/66; H03M1/74; H03M1/80; H03M1/802; H03M1/804
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
81 words
A method of performing analog to digital conversion using a capacitive array, comprising in sequence: terminating acquisition of an analog input signal upon occurrence of a start conversion command; successively approximating a digital value of said analog input signal using said capacitive array; fixing said digital value upon completion of said successive approximation; discharging said capacitive array; and initiating acquisition of an analog input signal after said discharging said capacitive array and before a leading edge of said start conversion command.
Claim 2
Independent Claim
81 words
A method of performing analog to digital conversion using a capacitive array, comprising in sequence: terminating acquisition of an analog input signal upon occurrence of a start conversion command; successively approximating a digital value of said analog input signal using said capacitive array; fixing said digital value upon completion of said successive approximation; discharging said capacitive array; and initiating acquisition of an analog input signal after said discharging said capacitive array and before a leading edge of said start conversion command.
Claim 3
Dependent Claim
27 words
A method according to claim 1, including, following said discharging step, sampling and holding an offset of a comparator connected to an output of said capacitive array.
Claim 4
Dependent Claim
15 words
A method according to claim 1, wherein said approximating begins immediately after termination of acquisition.
Claim 5
Dependent Claim
47 words
A method according to claim 1, wherein upon occurrence of said start conversion command, an input of said capacitive array is disconnected from an analog signal and connected to a reference signal and a first terminal of each capacitor of said capacitive array is connected to ground.
Claim 6
Dependent Claim
31 words
A method according to claim 4, including connecting said input of said capacitive array to said analog signal from termination of said approximating step to occurrence of said start conversion command.
Claim 7
Dependent Claim
27 words
A method according to claim 5, including, following said discharging step, sampling and holding an offset of a comparator connected to an output of said capacitive array.
Claim 8
Dependent Claim
31 words
A method according to claim 1, including connecting an input of said capacitive array to said analog signal from termination of said approximating step to occurrence of said start conversion command.
Claim 9
Dependent Claim
16 words
A method according to claim 1, wherein said capacitive array is a binary weighted capacitive array.
Claim 10
Dependent Claim
216 words
In an analog to digital converter having an analog input means, a capacitive digital to analog converter means, a successive approximation register means, comparator means for comparing an analog input signal acquired by said analog input means with an analog signal converted by said converter means from a digital signal from said register means, digital output means and control means responsive to a start conversion command for controlling the sequence of acquisition of an input analog signal by said analog input means, discharging a capacitor array of said converter, successive approximation of a digital value of an acquired analog input signal by said converter, comparator and register means and outputting digital value on said digital output means, the improvement comprising said control means which in response to a start conversion command produces in sequence: termination of acquisition of an input analog signal by said analog input means; successively approximating a digital value of said acquired analog input signal by said converter, comparator and register means; outputting said digital value on said digital output upon completion of said successive approximation; discharging said capacitor array of said converter means; and initiating acquisition of an input analog signal by said analog input means after said discharging said capacitive array and before a leading edge of a start conversion command.
Claim 11
Dependent Claim
216 words
In an analog to digital converter having an analog input means, a capacitive digital to analog converter means, a successive approximation register means, comparator means for comparing an analog input signal acquired by said analog input means with an analog signal converted by said converter means from a digital signal from said register means, digital output means and control means responsive to a start conversion command for controlling the sequence of acquisition of an input analog signal by said analog input means, discharging a capacitor array of said converter, successive approximation of a digital value of an acquired analog input signal by said converter, comparator and register means and outputting digital value on said digital output means, the improvement comprising said control means which in response to a start conversion command produces in sequence: termination of acquisition of an input analog signal by said analog input means; successively approximating a digital value of said acquired analog input signal by said converter, comparator and register means; outputting said digital value on said digital output upon completion of said successive approximation; discharging said capacitor array of said converter means; and initiating acquisition of an input analog signal by said analog input means after said discharging said capacitive array and before a leading edge of a start conversion command.
Claim 12
Dependent Claim
30 words
A converter according to claim 9, including offset means for determining an offset of said comparator means, and said control means activates said offset means after discharging said capacitor array.
Claim 13
Dependent Claim
19 words
A converter according to claim 9, wherein said control means initiates said successive approximation immediately after termination of acquisition.
Claim 14
Dependent Claim
112 words
A converter according to claim 9, wherein: said analog input means includes an input port and first switch means for connecting an input terminal of said capacitor array to said input port or a reference value; said converter means includes a second switch means for individually connecting a input terminal of each capacitor in said capacitor array to ground or to said input terminal of said capacitor array; and said control means controls said first and second switch means to disconnect said input terminal of said capacitor array from said input port and connecting said first terminal of each of said capacitors to ground to terminate acquisition of an analog input signal.
Claim 15
Dependent Claim
56 words
A converter according to claim 12, wherein said control means controls said first and second switch means to connect said input terminal of each of said capacitor array to said reference value and selectively connecting said first terminal of said capacitor to either ground or said input terminal of said capacitor array during said successive approximation.
Claim 16
Dependent Claim
41 words
A converter according to claim 12, wherein said control means controls said first switch means to connect said input terminal of said capacitor array to said input port from termination of said successive approximation to occurrence of said start conversion command.
Claim 17
Dependent Claim
46 words
A converter according to claim 14, wherein said control means controls said second switch means to connect said first terminal of said capacitors to said input terminal of said capacitor array from termination of discharging said capacitors to termination of acquisition of said analog input signal.
Claim 18
Dependent Claim
16 words
A converter according to claim 9, wherein said capacitor array is a binary weighted capacitive array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-31 | 1994-07-02 | 1995-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-31 | 1998-07-02 | 1999-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-31 | 2002-07-02 | 2003-01-01 | $7700.00 | Window Closed / Lapsed |