Arithmetic unit for exponential function

Claim 1

An arithmetic unit for carrying out sequentially arithmetic pseudo division and reverse-sequentially arithmetic pseudo multiplication according to algorithm based on Sequential Table Lookup method utilizing constant values 2 k xloge(1+2 -k ) so as to calculate value of exponential function e x -1 for a given value x, the unit comprising: generating means for sequentially generating the constant values 2 k xloge(1+2 -k ) from k=0 to k=m-1 where m is an positive integer number; an adder-subtracter controllable to selectively carry out arithmetic addition and subtraction; an output register connected to receive and store the arithmetic result from the adder-subtracter; a barrel shifter operative during the pseudo multiplication and connected to the output register for right-shifting a content thereof by shift bit count k where k=1, 2 . . . , m-2, m-1, m; a pair of input registers connected to the adder-subtracter for inputting thereinto their contents to be processed thereby, one of the input registers being connected to the output register for receiving therefrom an updated content thereof, the other input register being connected to the generating means for receiving therefrom the constant value 2 k xloge(1+2 -k ) during the pseudo division and to the barrel shifter for receiving therefrom the right-shifted content of the output register during the pseudo multiplication; and stack means connected to the output register for stacking in First-In, Last-Out basis sign bit of the content of the output register, the stack means being operative during the sequential arithmetic pseudo division for controlling the adder-subtracter according to the value of sign bit to carry out the subtraction of the content of the other input register from the content of said one input register, and being operative during the sequential arithmetic pseudo multiplication for controlling the adder-subtracter according to the value of sign bit to selectively carry out the addition of a value zero or the content of the other input register to the content of said one input register.