Monolithic pressure sensitive integrated circuit

Claim 2

A process for making a monolithic pressure sensitive integrated circuit comprising: forming on one surface of a monocrystalline semiconductor member a localized etch stop region; growing in turn over said one surface first and second epitaxial layers of mutually opposite conductivity types; said first epitaxial layer having a higher resistivity adjacent said substrate than adjacent said second epitaxial layer; forming buried layers between said first and second epitaxial layers; forming in said second epitaxial layer in the region overlying the etch stop a plurality of piezoresistors and in the surrounding region the remainder of the integrated circuit and interconnecting said remainder and the piezoresistors into the desired integrated circuit; and etching anisotropically the back surface of the element in the region underlying the element in the etch stop region to thin the element in the region underlying the piezoresistors.

Claim 3

A process for fabricating a monolithic pressure sensitive integrated circuit comprising the steps of: forming on one surface of a monocrystalline semiconductive member of relatively high resistivity a localized region of conductivity sufficiently high to serve as an etch-stop; forming over said surface a first epitaxial layer of one conductivity type and relatively high resistivity; forming in said epitaxial layer a surface region having the conductivity type opposite said one conductivity type and substantially overlying the etch-stop layer and a plurality of surface regions of both the one and the opposite conductivity types in surrounding regions; forming over said first epitaxial layer a second epitaxial layer of conductivity type opposite said one conductivity type; forming in said second epitaxial layer by a first doping step localized regions of the one conductivity type for serving as the piezoresistors in regions substantially overlying the periphery of the etch-stop layer, base zones of vertical transistors, emitter and collector zones of lateral transistors an p-n junction isolation barriers; forming in said second eptiaxial layer by a second doping step, localized regions of the opposite conductivity type for serving as the emitters of the vertical transistors, and doped collector connection regions for vertical transistors; interconnecting with metallization the piezoresistors and the vertical and lateral transistors in the second epitaxial layer into an integrated circuit; and forming in the back surface of the element a cavity aligned with the etch-stop layer for forming a diaphragm whose periphery underlies the piezoresistors.

Claim 4

A process for fabricating a monolithic pressure sensitive integrated circuit comprising the steps of: forming on one surface of a monocrystalline semiconductive member of relatively high resistivity a localized region of conductivity sufficiently high to serve as an etch-stop; forming over said surface a first epitaxial layer of one conductivity type and relatively high resistivity; forming in said epitaxial layer a surface region having the conductivity type opposite said one conductivity type and substantially overlying the etch-stop layer and a plurality of surface regions of both the one and the opposite conductivity types in surrounding regions; forming over said first epitaxial layer a second epitaxial layer of conductivity type opposite said one conductivity type; forming in said second epitaxial layer by a first doping step localized regions of the one conductivity type for serving as the piezoresistors in regions substantially overlying the periphery of the etch-stop layer, base zones of vertical transistors, emitter and collector zones of lateral transistors an p-n junction isolation barriers; forming in said second eptiaxial layer by a second doping step, localized regions of the opposite conductivity type for serving as the emitters of the vertical transistors, and doped collector connection regions for vertical transistors; interconnecting with metallization the piezoresistors and the vertical and lateral transistors in the second epitaxial layer into an integrated circuit; and forming in the back surface of the element a cavity aligned with the etch-stop layer for forming a diaphragm whose periphery underlies the piezoresistors.

Claim 5

The process of claim 2 in which the semiconductive material of the member is silicon and the front and back surfaces of the member lie along <100> crystal planes.

Claim 6

The process of claim 3 in which the first epitaxial layer is first partially grown without added doping and then grown with added doping.